From patchwork Mon Jan 11 18:21:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiri Kuzin X-Patchwork-Id: 86338 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6563A09FF; Mon, 11 Jan 2021 19:22:37 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B34D7140FED; Mon, 11 Jan 2021 19:22:15 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by mails.dpdk.org (Postfix) with ESMTP id EF329140FE6 for ; Mon, 11 Jan 2021 19:22:12 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from shirik@nvidia.com) with SMTP; 11 Jan 2021 20:22:10 +0200 Received: from nvidia.com (c-141-254-1-005.mtl.labs.mlnx [10.141.254.5]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 10BIM0fW011077; Mon, 11 Jan 2021 20:22:10 +0200 From: Shiri Kuzin To: dev@dpdk.org Cc: viacheslavo@nvidia.com, andrew.rybchenko@oktetlabs.ru, olivier.matz@6wind.com, orika@nvidia.com, ferruh.yigit@intel.com, thomas@monjalon.net, rasland@nvidia.com Date: Mon, 11 Jan 2021 20:21:52 +0200 Message-Id: <20210111182153.9972-6-shirik@nvidia.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210111182153.9972-1-shirik@nvidia.com> References: <20201228194432.30512-1-shirik@nvidia.com> <20210111182153.9972-1-shirik@nvidia.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 5/6] net/mlx5: add GTP PSC item translation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds the translation function which sets the qfi, PDU type. The next extension header which indicates the following extension header type is set to 0x85 - a PDU session container. Signed-off-by: Shiri Kuzin Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow.h | 3 ++ drivers/net/mlx5/mlx5_flow_dv.c | 86 +++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index e54412e07b..c25b100945 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -357,6 +357,9 @@ enum mlx5_feature_name { /* GTP extension header max PDU type value. */ #define MLX5_GTP_EXT_MAX_PDU_TYPE 15 +/* GTP extension header PDU type shift. */ +#define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) + /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */ #define MLX5_IPV4_FRAG_OFFSET_MASK \ (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index d11f4eb4b8..860ef9aa01 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7930,6 +7930,82 @@ flow_dv_translate_item_gtp(void *matcher, void *key, rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid)); } +/** + * Add GTP PSC item to matcher. + * + * @param[in, out] matcher + * Flow matcher. + * @param[in, out] key + * Flow matcher value. + * @param[in] item + * Flow pattern to translate. + */ +static int +flow_dv_translate_item_gtp_psc(void *matcher, void *key, + const struct rte_flow_item *item) +{ + const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask; + const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec; + void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher, + misc_parameters_3); + void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3); + union { + uint32_t w32; + struct { + uint16_t seq_num; + uint8_t npdu_num; + uint8_t next_ext_header_type; + }; + } dw_2; + uint8_t gtp_flags; + + /* Always set E-flag match on one, regardless of GTP item settings. */ + gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags); + gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags); + gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags); + gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags); + /*Set next extension header type. */ + dw_2.seq_num = 0; + dw_2.npdu_num = 0; + dw_2.next_ext_header_type = 0xff; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2, + rte_cpu_to_be_32(dw_2.w32)); + dw_2.seq_num = 0; + dw_2.npdu_num = 0; + dw_2.next_ext_header_type = 0x85; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2, + rte_cpu_to_be_32(dw_2.w32)); + if (gtp_psc_v) { + union { + uint32_t w32; + struct { + uint8_t len; + uint8_t type_flags; + uint8_t qfi; + uint8_t reserved; + }; + } dw_0; + + /*Set extension header PDU type and Qos. */ + if (!gtp_psc_m) + gtp_psc_m = &rte_flow_item_gtp_psc_mask; + dw_0.w32 = 0; + dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type); + dw_0.qfi = gtp_psc_m->qfi; + MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0, + rte_cpu_to_be_32(dw_0.w32)); + dw_0.w32 = 0; + dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type & + gtp_psc_m->pdu_type); + dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi; + MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0, + rte_cpu_to_be_32(dw_0.w32)); + } + return 0; +} + /** * Add eCPRI item to matcher and to the value. * @@ -10615,6 +10691,16 @@ flow_dv_translate(struct rte_eth_dev *dev, matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc); last_item = MLX5_FLOW_LAYER_GTP; break; + case RTE_FLOW_ITEM_TYPE_GTP_PSC: + ret = flow_dv_translate_item_gtp_psc(match_mask, + match_value, + items); + if (ret) + return rte_flow_error_set(error, -ret, + RTE_FLOW_ERROR_TYPE_ITEM, NULL, + "cannot create GTP PSC item"); + last_item = MLX5_FLOW_LAYER_GTP_PSC; + break; case RTE_FLOW_ITEM_TYPE_ECPRI: if (!mlx5_flex_parser_ecpri_exist(dev)) { /* Create it only the first time to be used. */