From patchwork Tue Jan 12 02:57:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ruifeng Wang X-Patchwork-Id: 86361 X-Patchwork-Delegate: david.marchand@redhat.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6706A04B5; Tue, 12 Jan 2021 03:58:13 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4999140CD7; Tue, 12 Jan 2021 03:58:13 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id 55085140CD7; Tue, 12 Jan 2021 03:58:12 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1291101E; Mon, 11 Jan 2021 18:58:11 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0C8E93F66E; Mon, 11 Jan 2021 18:58:07 -0800 (PST) From: Ruifeng Wang To: Harman Kalra , Santosh Shukla , Jerin Jacob Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, pbhagavatula@marvell.com, jerinj@marvell.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Tue, 12 Jan 2021 02:57:06 +0000 Message-Id: <20210112025709.1121523-4-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210112025709.1121523-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210112025709.1121523-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v3 3/5] net/octeontx: fix build with sve enabled X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Building with gcc 10.2 with SVE extension enabled got error: {standard input}: Assembler messages: {standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1' {standard input}:95: Error: selected processor does not support `ptrue p1.d,all' {standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5' {standard input}:137: Error: selected processor does not support `decb x1' This is because inline assembly code explicitly resets cpu model to not have SVE support. Thus SVE instructions generated by compiler auto vectorization got rejected by assembler. Added SVE to the cpu model specified by inline assembly for SVE support. Not replacing the inline assembly with C atomics because the driver relies on specific LSE instruction to interface to co-processor [1]. Fixes: f0c7bb1bf778 ("net/octeontx/base: add octeontx IO operations") Cc: jerinj@marvell.com Cc: stable@dpdk.org [1] https://mails.dpdk.org/archives/dev/2021-January/196092.html Signed-off-by: Ruifeng Wang Reviewed-by: Jerin Jacob --- v3: Keep inline assembly and add sve extension to fix issue. (Pavan) drivers/net/octeontx/base/octeontx_io.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/octeontx/base/octeontx_io.h b/drivers/net/octeontx/base/octeontx_io.h index 04b9ce191..d0b9cfbc6 100644 --- a/drivers/net/octeontx/base/octeontx_io.h +++ b/drivers/net/octeontx/base/octeontx_io.h @@ -52,6 +52,11 @@ do { \ #endif #if defined(RTE_ARCH_ARM64) +#if defined(__ARM_FEATURE_SVE) +#define __LSE_PREAMBLE " .cpu generic+lse+sve\n" +#else +#define __LSE_PREAMBLE " .cpu generic+lse\n" +#endif /** * Perform an atomic fetch-and-add operation. */ @@ -61,7 +66,7 @@ octeontx_reg_ldadd_u64(void *addr, int64_t off) uint64_t old_val; __asm__ volatile( - " .cpu generic+lse\n" + __LSE_PREAMBLE " ldadd %1, %0, [%2]\n" : "=r" (old_val) : "r" (off), "r" (addr) : "memory"); @@ -98,12 +103,13 @@ octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[], /* LDEOR initiates atomic transfer to I/O device */ __asm__ volatile( - " .cpu generic+lse\n" + __LSE_PREAMBLE " ldeor xzr, %0, [%1]\n" : "=r" (result) : "r" (ioreg_va) : "memory"); } while (!result); } +#undef __LSE_PREAMBLE #else static inline uint64_t