[v3,5/5] config: add Arm Neoverse N2
diff mbox series

Message ID 20210112025709.1121523-6-ruifeng.wang@arm.com
State Accepted
Delegated to: David Marchand
Headers show
Series
  • lpm lookup with sve support
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Commit Message

Ruifeng Wang Jan. 12, 2021, 2:57 a.m. UTC 
Add Arm Neoverse N2 cpu support.

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
---
v3:
Changed arch extension from sve to sve2 as N2 supports sve2. (Honnappa)

 config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
 config/arm/meson.build        | 11 ++++++++++-
 2 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 config/arm/arm64_n2_linux_gcc

Comments

Jerin Jacob Jan. 12, 2021, 4:44 a.m. UTC | #1 
On Tue, Jan 12, 2021 at 8:28 AM Ruifeng Wang <ruifeng.wang@arm.com> wrote:
>
> Add Arm Neoverse N2 cpu support.
>
> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>


Acked-by: Jerin Jacob <jerinj@marvell.com>


> ---
> v3:
> Changed arch extension from sve to sve2 as N2 supports sve2. (Honnappa)
>
>  config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
>  config/arm/meson.build        | 11 ++++++++++-
>  2 files changed, 27 insertions(+), 1 deletion(-)
>  create mode 100644 config/arm/arm64_n2_linux_gcc
>
> diff --git a/config/arm/arm64_n2_linux_gcc b/config/arm/arm64_n2_linux_gcc
> new file mode 100644
> index 000000000..78f6f3e2b
> --- /dev/null
> +++ b/config/arm/arm64_n2_linux_gcc
> @@ -0,0 +1,17 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> +pcap-config = ''
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x41'
> +implementor_pn = '0xd49'
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 42b4e43c7..5fd1c40a0 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -89,6 +89,14 @@ flags_n1generic_extra = [
>         ['RTE_MAX_NUMA_NODES', 1],
>         ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
>         ['RTE_LIBRTE_VHOST_NUMA', false]]
> +flags_n2generic_extra = [
> +       ['RTE_MACHINE', '"neoverse-n2"'],
> +       ['RTE_MAX_LCORE', 64],
> +       ['RTE_CACHE_LINE_SIZE', 64],
> +       ['RTE_ARM_FEATURE_ATOMICS', true],
> +       ['RTE_USE_C11_MEM_MODEL', true],
> +       ['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> +       ['RTE_LIBRTE_VHOST_NUMA', false]]
>
>  machine_args_generic = [
>         ['default', ['-march=armv8-a+crc', '-moutline-atomics']],
> @@ -100,7 +108,8 @@ machine_args_generic = [
>         ['0xd09', ['-mcpu=cortex-a73']],
>         ['0xd0a', ['-mcpu=cortex-a75']],
>         ['0xd0b', ['-mcpu=cortex-a76']],
> -       ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra]]
> +       ['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra],
> +       ['0xd49', ['-march=armv8.5-a+crypto+sve2'], flags_n2generic_extra]]
>
>  machine_args_cavium = [
>         ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> --
> 2.25.1
>
Honnappa Nagarahalli Jan. 13, 2021, 2:08 a.m. UTC | #2 
<snip>

> 
> Add Arm Neoverse N2 cpu support.
> 
> Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Looks good

Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> ---
> v3:
> Changed arch extension from sve to sve2 as N2 supports sve2. (Honnappa)
> 
>  config/arm/arm64_n2_linux_gcc | 17 +++++++++++++++++
>  config/arm/meson.build        | 11 ++++++++++-
>  2 files changed, 27 insertions(+), 1 deletion(-)  create mode 100644
> config/arm/arm64_n2_linux_gcc
> 
> diff --git a/config/arm/arm64_n2_linux_gcc
> b/config/arm/arm64_n2_linux_gcc new file mode 100644 index
> 000000000..78f6f3e2b
> --- /dev/null
> +++ b/config/arm/arm64_n2_linux_gcc
> @@ -0,0 +1,17 @@
> +[binaries]
> +c = 'aarch64-linux-gnu-gcc'
> +cpp = 'aarch64-linux-gnu-cpp'
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> +pcap-config = ''
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv8-a'
> +endian = 'little'
> +
> +[properties]
> +implementor_id = '0x41'
> +implementor_pn = '0xd49'
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> 42b4e43c7..5fd1c40a0 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -89,6 +89,14 @@ flags_n1generic_extra = [
>  	['RTE_MAX_NUMA_NODES', 1],
>  	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
>  	['RTE_LIBRTE_VHOST_NUMA', false]]
> +flags_n2generic_extra = [
> +	['RTE_MACHINE', '"neoverse-n2"'],
> +	['RTE_MAX_LCORE', 64],
> +	['RTE_CACHE_LINE_SIZE', 64],
> +	['RTE_ARM_FEATURE_ATOMICS', true],
> +	['RTE_USE_C11_MEM_MODEL', true],
> +	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
> +	['RTE_LIBRTE_VHOST_NUMA', false]]
> 
>  machine_args_generic = [
>  	['default', ['-march=armv8-a+crc', '-moutline-atomics']], @@ -100,7
> +108,8 @@ machine_args_generic = [
>  	['0xd09', ['-mcpu=cortex-a73']],
>  	['0xd0a', ['-mcpu=cortex-a75']],
>  	['0xd0b', ['-mcpu=cortex-a76']],
> -	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> flags_n1generic_extra]]
> +	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'],
> flags_n1generic_extra],
> +	['0xd49', ['-march=armv8.5-a+crypto+sve2'], flags_n2generic_extra]]
> 
>  machine_args_cavium = [
>  	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],
> --
> 2.25.1

Patch
diff mbox series 

diff --git a/config/arm/arm64_n2_linux_gcc b/config/arm/arm64_n2_linux_gcc
new file mode 100644
index 000000000..78f6f3e2b
--- /dev/null
+++ b/config/arm/arm64_n2_linux_gcc
@@ -0,0 +1,17 @@ 
+[binaries]
+c = 'aarch64-linux-gnu-gcc'
+cpp = 'aarch64-linux-gnu-cpp'
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv8-a'
+endian = 'little'
+
+[properties]
+implementor_id = '0x41'
+implementor_pn = '0xd49'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 42b4e43c7..5fd1c40a0 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -89,6 +89,14 @@  flags_n1generic_extra = [
 	['RTE_MAX_NUMA_NODES', 1],
 	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
 	['RTE_LIBRTE_VHOST_NUMA', false]]
+flags_n2generic_extra = [
+	['RTE_MACHINE', '"neoverse-n2"'],
+	['RTE_MAX_LCORE', 64],
+	['RTE_CACHE_LINE_SIZE', 64],
+	['RTE_ARM_FEATURE_ATOMICS', true],
+	['RTE_USE_C11_MEM_MODEL', true],
+	['RTE_EAL_NUMA_AWARE_HUGEPAGES', false],
+	['RTE_LIBRTE_VHOST_NUMA', false]]
 
 machine_args_generic = [
 	['default', ['-march=armv8-a+crc', '-moutline-atomics']],
@@ -100,7 +108,8 @@  machine_args_generic = [
 	['0xd09', ['-mcpu=cortex-a73']],
 	['0xd0a', ['-mcpu=cortex-a75']],
 	['0xd0b', ['-mcpu=cortex-a76']],
-	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra]]
+	['0xd0c', ['-march=armv8.2-a+crypto', '-mcpu=neoverse-n1'], flags_n1generic_extra],
+	['0xd49', ['-march=armv8.5-a+crypto+sve2'], flags_n2generic_extra]]
 
 machine_args_cavium = [
 	['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']],