[v5,8/8] doc: update GENEVE TLV option support
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Message ID 20210112140241.15914-9-shirik@nvidia.com
State Superseded
Delegated to: Ferruh Yigit
Headers show
Series
  • ethdev: introduce GENEVE header TLV option item
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Commit Message

Shiri Kuzin Jan. 12, 2021, 2:02 p.m. UTC
GENEVE TLV option support added to mlx5 PMD.

The limitations and support were updated in
documentation.

Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 doc/guides/nics/mlx5.rst               | 23 ++++++++++++++++++++++-
 doc/guides/rel_notes/release_21_02.rst |  8 ++++++++
 2 files changed, 30 insertions(+), 1 deletion(-)

Patch
diff mbox series

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 3bda0f8417..5f2b42b979 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -98,6 +98,7 @@  Features
 - Hardware LRO.
 - Hairpin.
 - Multiple-thread flow insertion.
+- Matching on Geneve TLV option header with raw encap/decap action.
 
 Limitations
 -----------
@@ -175,7 +176,18 @@  Limitations
      - OAM
      - protocol type
      - options length
-       Currently, the only supported options length value is 0.
+
+- Match on Geneve TLv option is supported on the following fields:
+     - Class
+     - Type
+     - Length
+     - Data
+
+  Only one Class/Type/Length Geneve TLV option is supported per shared device.
+  Class/Type/Length fields must be specified as well as masks.
+  Class/Type/Length specified masks must be full.
+  Matching Geneve TLV option without specifying data is not supported.
+  Matching Geneve TLV option with data & mask == 0 is not supported.
 
 - VF: flow rules created on VF devices can only match traffic targeted at the
   configured MAC addresses (see ``rte_eth_dev_mac_addr_add()``).
@@ -1022,6 +1034,10 @@  Below are some firmware configurations listed.
    or
    FLEX_PARSER_PROFILE_ENABLE=1
 
+- enable Geneve TLV option flow matching::
+
+   FLEX_PARSER_PROFILE_ENABLE=0
+
 - enable GTP flow matching::
 
    FLEX_PARSER_PROFILE_ENABLE=3
@@ -1501,6 +1517,11 @@  Supported hardware offloads
    |                       | |  rdma-core 32 | | rdma-core 32  |
    |                       | |  ConnectX-6 Dx| | ConnectX-6 Dx |
    +-----------------------+-----------------+-----------------+
+   | Encapsulation         | | DPDK 21.02    | | DPDK 21.02    |
+   | GENEVE TLV option     | | OFED 5.2      | | OFED 5.2      |
+   |                       | | rdma-core 34  | | rdma-core 34  |
+   |                       | | ConnectX-6 Dx | | ConnectX-6 Dx |
+   +-----------------------+-----------------+-----------------+
 
 Notes for metadata
 ------------------
diff --git a/doc/guides/rel_notes/release_21_02.rst b/doc/guides/rel_notes/release_21_02.rst
index 706cbf8f0c..1ac0232350 100644
--- a/doc/guides/rel_notes/release_21_02.rst
+++ b/doc/guides/rel_notes/release_21_02.rst
@@ -55,6 +55,14 @@  New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Updated Mellanox mlx5 driver.**
+
+  Updated the Mellanox mlx5 driver with new features and improvements, including:
+
+  * **Added GENEVE TLV option in rte_flow.**
+
+  Added support for matching GENEVE TLV option and raw encap/decap of GENEVE
+  TLV option.
 
 Removed Items
 -------------