From patchwork Thu Jul 27 09:31:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 129709 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2EE6B42F5B; Thu, 27 Jul 2023 11:31:22 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id AA4E640693; Thu, 27 Jul 2023 11:31:21 +0200 (CEST) Received: from mgamail.intel.com (unknown [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 448F340041 for ; Thu, 27 Jul 2023 11:31:19 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690450279; x=1721986279; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=zHqbjWsWM8oRifRPbtqhEmslTtCetBNrvQFAqo5FKeg=; b=XXXQkmUECGzmbj4f8BhXZ0fcv1jEuEKPqLBDThlOHlfMbvy1/z6es9X+ Ad1Hf5roipKjmGneNMeQrg/Uu+VfFbe47n3Iov6uBPBSGwQgyp1rtxUNE 8SvlPuP0R0YQGXYceNbmhoatrbQcod5rR8X265TNUHPOdbVkEElmW5FzD GPG28saLN8MC4Qp10BgFC00uQrT1r23zseiikugAjCEC7GlH7P12cLItC 5ezlImIyv3K/bkYGIw9rKqNgEc9429lf4mL1O2049UP9kmsGDHmciKkOi 4ofuH5DTHfMVB3b/WXkKNZHPNHh9MxithX4FlENgKU5xV34OF146xLyS8 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10783"; a="434537433" X-IronPort-AV: E=Sophos;i="6.01,234,1684825200"; d="scan'208";a="434537433" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jul 2023 02:31:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10783"; a="756584455" X-IronPort-AV: E=Sophos;i="6.01,234,1684825200"; d="scan'208";a="756584455" Received: from silpixa00401385.ir.intel.com ([10.237.214.14]) by orsmga008.jf.intel.com with ESMTP; 27 Jul 2023 02:31:16 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson Subject: [PATCH 0/2] simplify building x86 code with AVX2 support Date: Thu, 27 Jul 2023 10:31:05 +0100 Message-Id: <20230727093107.7242-1-bruce.richardson@intel.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Inside our optimized vector drivers (and libs), there were always build time checks for various levels of instruction set support, most notably AVX2 and AVX-512 on x86 systems. One of the checks done in each case was verifying that the compiler used was able to generate AVX code appropriately. However, since this was originally done, our minimum compiler support has been updated and so we no longer need to check this - all supported compilers can generate AVX2. This allows us to simplify the build logic for the x86 vector code. In future, we can do similarly for AVX-512. Bruce Richardson (2): build/x86: remove conditional checks for AVX2 support build: remove unnecessary AVX2 compiler flag drivers/net/bnxt/bnxt_ethdev.c | 8 ++++---- drivers/net/bnxt/bnxt_rxr.h | 2 +- drivers/net/bnxt/bnxt_txr.h | 2 +- drivers/net/bnxt/meson.build | 26 +++++++++---------------- drivers/net/enic/meson.build | 10 +++------- drivers/net/i40e/i40e_rxtx.c | 14 ++++--------- drivers/net/i40e/meson.build | 22 ++++++--------------- drivers/net/iavf/iavf_rxtx_vec_common.h | 2 +- drivers/net/iavf/meson.build | 22 ++++++--------------- drivers/net/ice/meson.build | 21 ++++++-------------- lib/acl/meson.build | 23 +++++----------------- lib/acl/rte_acl.c | 10 +++------- 12 files changed, 49 insertions(+), 113 deletions(-) --- 2.39.2