From patchwork Mon Feb 26 13:03:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nayak, Nishikanta" X-Patchwork-Id: 686 Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E738843BEF; Mon, 26 Feb 2024 14:03:50 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 72B0D42E18; Mon, 26 Feb 2024 14:03:50 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.16]) by mails.dpdk.org (Postfix) with ESMTP id DCDD140144 for ; Mon, 26 Feb 2024 14:03:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708952628; x=1740488628; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WOwIUIQFwV/+8l+kbPIedREijfYirbQRvK4v8WFrmj4=; b=RLHAd4qA5jQNaw8XX7jwpHWkuuTWt1fzaARqvF9sMZItMFV+NoaKSnHo +BipfQlJ/7Vm96YkQPsaVPyKvQIe1Pp/YlXoGjI1Qa/XcVz3/2wuklisp MF6oEcpISLA0eWGGyfiBzI/THOwADN6Xp0dDSM9je4RBZJ2uk/I8HATVY +MhHu7+tSzjtfmUrC5yreUAaU5Zrt/CxOElpHdwrHaE2fOl/28lcuLBFD yVerKjqgCmiMZgiCraB59+5AWYNO/F6T42VQAn9MOrlgMkq1UaS06oqC9 vMuhwEqIwOQ2/nviFeen29/IPaEdLxcfnogF0D931hquqcUykNVNnJMV+ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10995"; a="3367268" X-IronPort-AV: E=Sophos;i="6.06,185,1705392000"; d="scan'208";a="3367268" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Feb 2024 05:03:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,185,1705392000"; d="scan'208";a="6695406" Received: from silpixa00401797.ir.intel.com (HELO silpixa00400355.ger.corp.intel.com) ([10.237.222.113]) by orviesa009.jf.intel.com with ESMTP; 26 Feb 2024 05:03:46 -0800 From: Nishikant Nayak To: dev@dpdk.org Cc: ciara.power@intel.com, kai.ji@intel.com, arkadiuszx.kusztal@intel.com, rakesh.s.joshi@intel.com, Nishikant Nayak Subject: [PATCH v2 0/4] add QAT GEN LCE device Date: Mon, 26 Feb 2024 13:03:38 +0000 Message-Id: <20240226130342.4115292-1-nishikanta.nayak@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231220132616.318983-1-nishikanta.nayak@intel.com> References: <20231220132616.318983-1-nishikanta.nayak@intel.com> MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patchset adds a new QAT LCE device. The device currently only supports symmetric crypto, and only the AES-GCM algorithm. v2: - Renamed device from GEN 5 to GEN LCE. - Removed unused code. - Updated macro names. Nishikant Nayak (4): common/qat: add files specific to GEN LCE common/qat: update common driver to support GEN LCE crypto/qat: update headers for GEN LCE support test/cryptodev: add tests for GCM with AAD .mailmap | 1 + app/test/test_cryptodev.c | 48 ++- app/test/test_cryptodev_aead_test_vectors.h | 62 ++++ drivers/common/qat/dev/qat_dev_gen_lce.c | 306 ++++++++++++++++ drivers/common/qat/meson.build | 2 + .../qat/qat_adf/adf_transport_access_macros.h | 1 + .../adf_transport_access_macros_gen_lce.h | 51 +++ .../adf_transport_access_macros_gen_lcevf.h | 48 +++ drivers/common/qat/qat_adf/icp_qat_fw.h | 34 ++ drivers/common/qat/qat_adf/icp_qat_fw_la.h | 59 +++- drivers/common/qat/qat_common.h | 1 + drivers/common/qat/qat_device.c | 9 + .../crypto/qat/dev/qat_crypto_pmd_gen_lce.c | 329 ++++++++++++++++++ drivers/crypto/qat/qat_sym.c | 16 +- drivers/crypto/qat/qat_sym.h | 66 +++- drivers/crypto/qat/qat_sym_session.c | 62 +++- drivers/crypto/qat/qat_sym_session.h | 10 +- 17 files changed, 1089 insertions(+), 16 deletions(-) create mode 100644 drivers/common/qat/dev/qat_dev_gen_lce.c create mode 100644 drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lce.h create mode 100644 drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lcevf.h create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen_lce.c