mbox series

[0/2] crypto/mlx5: optimize AES-GCM IPsec operation

Message ID 20240530072413.1602343-1-suanmingm@nvidia.com (mailing list archive)
Headers
Series crypto/mlx5: optimize AES-GCM IPsec operation |

Message

Suanming Mou May 30, 2024, 7:24 a.m. UTC 
To optimize AES-GCM IPsec operation within crypto/mlx5,
the DPDK API typically supplies AES_GCM AAD/Payload/Digest
in separate locations, potentially disrupting their
contiguous layout. In cases where the memory layout fails
to meet hardware (HW) requirements, an UMR WQE is initiated
ahead of the GCM's GGA WQE to establish a continuous
AAD/Payload/Digest virtual memory space for the HW MMU.

For IPsec scenarios, where the memory layout consistently
adheres to the fixed order of AAD/IV/Payload/Digest,
directly shrinking memory for AAD proves more efficient
than preparing a UMR WQE. To address this, a new devarg
"crypto_mode" with mode "ipsec_opt" is introduced in the
commit, offering an optimization hint specifically for
IPsec cases. When enabled, the PMD copies AAD directly
before Payload in the enqueue_burst function instead of
employing the UMR WQE. Subsequently, in the dequeue_burst
function, the overridden IV before Payload is restored
from the GGA WQE. It's crucial for users to avoid utilizing
the input mbuf data during processing.

Suanming Mou (2):
  crypto/mlx5: optimize AES-GCM IPsec operation
  crypto/mlx5: add out of place mode for IPsec operation

 doc/guides/cryptodevs/mlx5.rst         |  23 +++
 doc/guides/rel_notes/release_24_07.rst |   4 +
 drivers/crypto/mlx5/mlx5_crypto.c      |  22 ++-
 drivers/crypto/mlx5/mlx5_crypto.h      |  19 ++
 drivers/crypto/mlx5/mlx5_crypto_gcm.c  | 245 +++++++++++++++++++++++--
 5 files changed, 292 insertions(+), 21 deletions(-)

Comments

Suanming Mou June 13, 2024, 6:44 a.m. UTC | #1 
Hi Akhil,

Sorry, I just noticed seems you were not added to the list by maintainer script.
Can you please take a look at the series when available.

Thanks，
Suanming

> -----Original Message-----
> From: Suanming Mou <suanmingm@nvidia.com>
> Sent: Thursday, May 30, 2024 3:24 PM
> Cc: dev@dpdk.org
> Subject: [PATCH 0/2] crypto/mlx5: optimize AES-GCM IPsec operation
> 
> To optimize AES-GCM IPsec operation within crypto/mlx5, the DPDK API typically
> supplies AES_GCM AAD/Payload/Digest in separate locations, potentially
> disrupting their contiguous layout. In cases where the memory layout fails to
> meet hardware (HW) requirements, an UMR WQE is initiated ahead of the GCM's
> GGA WQE to establish a continuous AAD/Payload/Digest virtual memory space
> for the HW MMU.
> 
> For IPsec scenarios, where the memory layout consistently adheres to the fixed
> order of AAD/IV/Payload/Digest, directly shrinking memory for AAD proves more
> efficient than preparing a UMR WQE. To address this, a new devarg
> "crypto_mode" with mode "ipsec_opt" is introduced in the commit, offering an
> optimization hint specifically for IPsec cases. When enabled, the PMD copies AAD
> directly before Payload in the enqueue_burst function instead of employing the
> UMR WQE. Subsequently, in the dequeue_burst function, the overridden IV
> before Payload is restored from the GGA WQE. It's crucial for users to avoid
> utilizing the input mbuf data during processing.
> 
> Suanming Mou (2):
>   crypto/mlx5: optimize AES-GCM IPsec operation
>   crypto/mlx5: add out of place mode for IPsec operation
> 
>  doc/guides/cryptodevs/mlx5.rst         |  23 +++
>  doc/guides/rel_notes/release_24_07.rst |   4 +
>  drivers/crypto/mlx5/mlx5_crypto.c      |  22 ++-
>  drivers/crypto/mlx5/mlx5_crypto.h      |  19 ++
>  drivers/crypto/mlx5/mlx5_crypto_gcm.c  | 245
> +++++++++++++++++++++++--
>  5 files changed, 292 insertions(+), 21 deletions(-)
> 
> --
> 2.34.1
Akhil Goyal June 13, 2024, 6:02 p.m. UTC | #2 
> Hi Akhil,
> 
> Sorry, I just noticed seems you were not added to the list by maintainer script.
> Can you please take a look at the series when available.
> 
Please resend. CI is complaining about apply failure.
Suanming Mou June 14, 2024, 12:30 a.m. UTC | #3 
> -----Original Message-----
> From: Akhil Goyal <gakhil@marvell.com>
> Sent: Friday, June 14, 2024 2:02 AM
> To: Suanming Mou <suanmingm@nvidia.com>
> Cc: dev@dpdk.org
> Subject: RE: [PATCH 0/2] crypto/mlx5: optimize AES-GCM IPsec operation
> 
> > Hi Akhil,
> >
> > Sorry, I just noticed seems you were not added to the list by maintainer script.
> > Can you please take a look at the series when available.
> >
> Please resend. CI is complaining about apply failure.

Sure, thanks.