diff mbox series

[v1,25/30] net/i40e/base: add register definitions for FLU

Message ID	0ca1f6857169990fcb01368494aac786e9b500ee.1725270827.git.anatoly.burakov@intel.com (mailing list archive)
State	Accepted
Delegated to:	Bruce Richardson
Headers	From: Anatoly Burakov <anatoly.burakov@intel.com> To: dev@dpdk.org Cc: bruce.richardson@intel.com Subject: [PATCH v1 25/30] net/i40e/base: add register definitions for FLU Date: Mon, 2 Sep 2024 10:54:37 +0100 Message-ID: <0ca1f6857169990fcb01368494aac786e9b500ee.1725270827.git.anatoly.burakov@intel.com> In-Reply-To: <cover.1725270827.git.anatoly.burakov@intel.com> References: <cover.1725270827.git.anatoly.burakov@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: dev-bounces@dpdk.org
Series	Update net/i40e base driver \| [v1,00/30] Update net/i40e base driver [v1,01/30] net/i40e/base: adjust whitespace [v1,02/30] net/i40e/base: strip all tags from code [v1,03/30] net/i40e/base: remove non-inclusive language [v1,04/30] net/i40e/base: remove unused variables [v1,05/30] net/i40e/base: don't set flags in i40e_init_shared_code [v1,06/30] net/i40e/base: fix misleading debug logs and comments [v1,07/30] net/i40e/base: add missing define to X710TL device check [v1,08/30] net/i40e/base: add new device ID to 25G device list [v1,09/30] net/i40e/base: fix setting MAC type for X722 [v1,10/30] net/i40e/base: add definitions for rx_err1 [v1,11/30] net/i40e/base: fix not blinking X722 with x557 PHY [v1,12/30] net/i40e/base: add VLAN field for input set [v1,13/30] net/i40e/base: allow reading LED blink setting [v1,14/30] net/i40e/base: do not load DDP packages with reserved track ID [v1,15/30] net/i40e/base: add DDP package type defines [v1,16/30] net/i40e/base: add X722 defines for input set mask [v1,17/30] net/i40e/base: improve typecasting [v1,18/30] net/i40e/base: add named and raw structs to rx desc [v1,19/30] net/i40e/base: align registers to the specification [v1,20/30] net/i40e/base: add PHY debug register dump [v1,21/30] net/i40e/base: make register dump read-only [v1,22/30] net/i40e/base: fix unchecked return value [v1,23/30] net/i40e/base: check loop bounds [v1,24/30] net/i40e/base: make semaphore timeout 32-bit [v1,25/30] net/i40e/base: add register definitions for FLU [v1,26/30] net/i40e/base: add NVM acquire with custom timeout [v1,27/30] net/i40e/base: change time variables from 64 bit to 32 bit [v1,28/30] net/i40e/base: add trace buffer reading dependencies [v1,29/30] net/i40e/base: add Shadow RAM pointer definition [v1,30/30] net/i40e: update base driver README

Checks

Context	Check	Description
ci/checkpatch	warning	coding style issues

Commit Message

Burakov, Anatoly Sept. 2, 2024, 9:54 a.m. UTC

From: Piotr Skajewski <piotrx.skajewski@intel.com>

These registers are relevant to MAC source pruning feature.

Signed-off-by: Piotr Skajewski <piotrx.skajewski@intel.com>
Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com>
---
 drivers/net/i40e/base/i40e_register.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff mbox series

Patch

diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h
index e8372575e4..beac70f8d6 100644
--- a/drivers/net/i40e/base/i40e_register.h
+++ b/drivers/net/i40e/base/i40e_register.h
@@ -2049,6 +2049,14 @@ 
 #define I40E_PRTPM_TLPIC              0x001E43C0 /* Reset: GLOBR */
 #define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
 #define I40E_PRTPM_TLPIC_ETLPIC_MASK  I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
+#define I40E_GL_PRE_FLU_MSK_PH1_H(_i)             (0x00269F20 + ((_i) * 4)) /* _i=0...6 */ /* Reset: CORER */
+#define I40E_GL_PRE_FLU_MSK_PH1_H_MAX_INDEX       6
+#define I40E_GL_PRE_FLU_MSK_PH1_H_MASK_HIGH_SHIFT 0
+#define I40E_GL_PRE_FLU_MSK_PH1_H_MASK_HIGH_MASK  I40E_MASK(0xFFFF, I40E_GL_PRE_FLU_MSK_PH1_H_MASK_HIGH_SHIFT)
+#define I40E_GL_PRE_FLU_MSK_PH1_L(_i)            (0x00269EE0 + ((_i) * 4)) /* _i=0...6 */ /* Reset: CORER */
+#define I40E_GL_PRE_FLU_MSK_PH1_L_MAX_INDEX      6
+#define I40E_GL_PRE_FLU_MSK_PH1_L_MASK_LOW_SHIFT 0
+#define I40E_GL_PRE_FLU_MSK_PH1_L_MASK_LOW_MASK  I40E_MASK(0xFFFFFFFF, I40E_GL_PRE_FLU_MSK_PH1_L_MASK_LOW_SHIFT)
 #define I40E_GL_PRS_FVBM(_i)                 (0x00269760 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */
 #define I40E_GL_PRS_FVBM_MAX_INDEX           3
 #define I40E_GL_PRS_FVBM_FV_BYTE_INDX_SHIFT  0