diff mbox

[dpdk-dev,1/5] ethdev: Add new config field to config VMDQ offload register

Message ID 1408932572-10343-2-git-send-email-changchun.ouyang@intel.com (mailing list archive)
State Superseded, archived
Headers

Commit Message

Ouyang Changchun Aug. 25, 2014, 2:09 a.m. UTC 
This patch adds new field of rx mode in VMDQ config; and set the register PFVML2FLT
for IXGBE PMD, this makes VMDQ receive multicast and broadcast packets.

Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com>
Acked-by: Huawei Xie <huawei.xie@intel.com>
Acked-by: Cunming Liang <cunming.liang@intel.com>

---
 lib/librte_ether/rte_ethdev.h     |  1 +
 lib/librte_pmd_ixgbe/ixgbe_rxtx.c | 16 ++++++++++++++++
 2 files changed, 17 insertions(+)
diff mbox

Patch

diff --git a/lib/librte_ether/rte_ethdev.h b/lib/librte_ether/rte_ethdev.h
index 50df654..f44dd2d 100644
--- a/lib/librte_ether/rte_ethdev.h
+++ b/lib/librte_ether/rte_ethdev.h
@@ -575,6 +575,7 @@  struct rte_eth_vmdq_rx_conf {
 	uint8_t default_pool; /**< The default pool, if applicable */
 	uint8_t enable_loop_back; /**< Enable VT loop back */
 	uint8_t nb_pool_maps; /**< We can have up to 64 filters/mappings */
+	uint32_t rx_mode; /**< RX mode for vmdq */
 	struct {
 		uint16_t vlan_id; /**< The vlan id of the received frame */
 		uint64_t pools;   /**< Bitmask of pools for packet rx */
diff --git a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
index dfc2076..9efdbfb 100644
--- a/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
+++ b/lib/librte_pmd_ixgbe/ixgbe_rxtx.c
@@ -3084,6 +3084,7 @@  ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
 	struct ixgbe_hw *hw;
 	enum rte_eth_nb_pools num_pools;
 	uint32_t mrqc, vt_ctl, vlanctrl;
+	uint32_t vmolr = 0;
 	int i;
 
 	PMD_INIT_FUNC_TRACE();
@@ -3106,6 +3107,21 @@  ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
 
 	IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
 
+	for (i = 0; i < (int)num_pools; i++) {
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
+			vmolr |= IXGBE_VMOLR_AUPE;
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
+			vmolr |= IXGBE_VMOLR_ROMPE;
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
+			vmolr |= IXGBE_VMOLR_ROPE;
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
+			vmolr |= IXGBE_VMOLR_BAM;
+		if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
+			vmolr |= IXGBE_VMOLR_MPE;
+
+		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
+	}
+
 	/* VLNCTRL: enable vlan filtering and allow all vlan tags through */
 	vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 	vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */