From patchwork Mon Sep 29 07:16:18 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ouyang Changchun X-Patchwork-Id: 627 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 38D2D7E49; Mon, 29 Sep 2014 09:10:41 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 2649C7E48 for ; Mon, 29 Sep 2014 09:10:37 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 29 Sep 2014 00:10:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.04,618,1406617200"; d="scan'208";a="610111908" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by orsmga002.jf.intel.com with ESMTP; 29 Sep 2014 00:17:10 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id s8T7H8UN013984; Mon, 29 Sep 2014 15:17:08 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id s8T7H64l028405; Mon, 29 Sep 2014 15:17:08 +0800 Received: (from couyang@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8T7H6Oj028401; Mon, 29 Sep 2014 15:17:06 +0800 From: Ouyang Changchun To: dev@dpdk.org Date: Mon, 29 Sep 2014 15:16:18 +0800 Message-Id: <1411974986-28137-11-git-send-email-changchun.ouyang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1411974986-28137-1-git-send-email-changchun.ouyang@intel.com> References: <1411974986-28137-1-git-send-email-changchun.ouyang@intel.com> Subject: [dpdk-dev] [PATCH v2 10/18] ixgbe: Modify time to wait in polling flash update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" It need wait for 5 ms for polling EEC register in IXGBE X540 share codes. Signed-off-by: Changchun Ouyang --- lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c index e47fb1d..ab38450 100644 --- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c +++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c @@ -726,7 +726,7 @@ STATIC s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) status = IXGBE_SUCCESS; break; } - usec_delay(5); + msec_delay(5); } if (i == IXGBE_FLUDONE_ATTEMPTS)