From patchwork Fri Dec 19 07:26:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Helin" X-Patchwork-Id: 2110 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 6A02D8043; Fri, 19 Dec 2014 08:27:04 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id ADBFC7F8C for ; Fri, 19 Dec 2014 08:27:01 +0100 (CET) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 18 Dec 2014 23:27:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,605,1413270000"; d="scan'208";a="640158474" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga001.fm.intel.com with ESMTP; 18 Dec 2014 23:27:00 -0800 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id sBJ7Qvbh002650; Fri, 19 Dec 2014 15:26:57 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id sBJ7QtKI015598; Fri, 19 Dec 2014 15:26:57 +0800 Received: (from hzhan75@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id sBJ7QtOR015594; Fri, 19 Dec 2014 15:26:55 +0800 From: Helin Zhang To: dev@dpdk.org Date: Fri, 19 Dec 2014 15:26:42 +0800 Message-Id: <1418974005-15536-5-git-send-email-helin.zhang@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1418974005-15536-1-git-send-email-helin.zhang@intel.com> References: <1418974005-15536-1-git-send-email-helin.zhang@intel.com> Subject: [dpdk-dev] [PATCH RFC 4/7] ethdev: fix of calculating the size of flow type mask array X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" It wrongly calculates the size of the flow type mask array. The fix is to align the flow type maximum index ID with the number of element bit width, and then divide the number of element bit width. Signed-off-by: Helin Zhang --- lib/librte_ether/rte_eth_ctrl.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/librte_ether/rte_eth_ctrl.h b/lib/librte_ether/rte_eth_ctrl.h index 4308eae..1c15ed0 100644 --- a/lib/librte_ether/rte_eth_ctrl.h +++ b/lib/librte_ether/rte_eth_ctrl.h @@ -398,6 +398,10 @@ enum rte_fdir_mode { RTE_FDIR_MODE_PERFECT, /**< Enable FDIR perfect filter mode. */ }; +#define UINT32_BIT (CHAR_BIT * sizeof(uint32_t)) +#define RTE_FLOW_TYPE_MASK_ARRAY_SIZE \ + (RTE_ALIGN(RTE_ETH_FLOW_TYPE_MAX, UINT32_BIT)/UINT32_BIT) + /** * A structure used to get the information of flow director filter. * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_INFO operation. @@ -412,7 +416,7 @@ struct rte_eth_fdir_info { uint32_t guarant_spc; /**< Guaranteed spaces.*/ uint32_t best_spc; /**< Best effort spaces.*/ /** Bit mask for every supported flow type. */ - uint32_t flow_types_mask[RTE_ETH_FLOW_TYPE_MAX / sizeof(uint32_t)]; + uint32_t flow_types_mask[RTE_FLOW_TYPE_MASK_ARRAY_SIZE]; uint32_t max_flexpayload; /**< Total flex payload in bytes. */ /** Flexible payload unit in bytes. Size and alignments of all flex payload segments should be multiplies of this value. */