From patchwork Fri Jul 17 03:46:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhe Tao X-Patchwork-Id: 6474 Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 0F4CB5A7A; Fri, 17 Jul 2015 05:47:09 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id E1A5F5A79 for ; Fri, 17 Jul 2015 05:47:06 +0200 (CEST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP; 16 Jul 2015 20:47:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,492,1432623600"; d="scan'208";a="749057818" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga001.fm.intel.com with ESMTP; 16 Jul 2015 20:47:05 -0700 Received: from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com [10.239.29.89]) by shvmail01.sh.intel.com with ESMTP id t6H3l3JQ022351; Fri, 17 Jul 2015 11:47:03 +0800 Received: from shecgisg004.sh.intel.com (localhost [127.0.0.1]) by shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id t6H3l0gu013764; Fri, 17 Jul 2015 11:47:02 +0800 Received: (from zhetao@localhost) by shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t6H3l0ow013760; Fri, 17 Jul 2015 11:47:00 +0800 From: Zhe Tao To: dev@dpdk.org Date: Fri, 17 Jul 2015 11:46:57 +0800 Message-Id: <1437104817-13578-1-git-send-email-zhe.tao@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1436870216-12926-1-git-send-email-zhe.tao@intel.com> References: <1436870216-12926-1-git-send-email-zhe.tao@intel.com> Subject: [dpdk-dev] [PATCH v2] Fix the endian issue for the i40e read&write registers functions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When using the Power big endian CPU for i40e NIC, the current i40e related registers operations will cause a problem, because the i40e registers are little endian which is inconsistent with big endian CPU. Add the conversion for the inconsistency. Signed-off-by: Zhe Tao --- PATCH v2: Edit the comments make it more clear PATCH v1: Add the endian conversion for registers operations. drivers/net/i40e/base/i40e_osdep.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/i40e/base/i40e_osdep.h b/drivers/net/i40e/base/i40e_osdep.h index 3ce8057..70d2721 100644 --- a/drivers/net/i40e/base/i40e_osdep.h +++ b/drivers/net/i40e/base/i40e_osdep.h @@ -122,10 +122,10 @@ do { \ ((volatile uint32_t *)((char *)(a)->hw_addr + (reg))) static inline uint32_t i40e_read_addr(volatile void *addr) { - return I40E_PCI_REG(addr); + return rte_le_to_cpu_32(I40E_PCI_REG(addr)); } #define I40E_PCI_REG_WRITE(reg, value) \ - do {I40E_PCI_REG((reg)) = (value);} while(0) + do { I40E_PCI_REG((reg)) = rte_cpu_to_le_32(value); } while (0) #define I40E_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_GLGEN_STAT) #define I40EVF_WRITE_FLUSH(a) I40E_READ_REG(a, I40E_VFGEN_RSTAT)