diff mbox

[dpdk-dev,v2,01/10] bnx2x: Set cache line based on build configuration

Message ID 1475144449-22176-1-git-send-email-3chas3@gmail.com (mailing list archive)
State Superseded, archived
Delegated to: Bruce Richardson
Headers

Commit Message

Chas Williams Sept. 29, 2016, 10:20 a.m. UTC 
  Correctly hint the cache line size.  Remove unused macros associated
with the cache line size.

Fixes: 540a211084a7 ("bnx2x: driver core")

Signed-off-by: Chas Williams <3chas3@gmail.com>
Acked-by: Harish Patil <harish.patil@qlogic.com>
---
 drivers/net/bnx2x/bnx2x.h | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

Comments

Ferruh Yigit Sept. 30, 2016, 10:53 a.m. UTC | #1 
Hi Chas,

On 9/29/2016 11:20 AM, Chas Williams wrote:
> Correctly hint the cache line size.  Remove unused macros associated
> with the cache line size.
> 
> Fixes: 540a211084a7 ("bnx2x: driver core")
> 
> Signed-off-by: Chas Williams <3chas3@gmail.com>
> Acked-by: Harish Patil <harish.patil@qlogic.com>
> ---

Thank you for the updated patch.

When sending next version of the patchset, can you please take care of
following too:

- patch title should be:
  "net/<driver>: all_lowercase_except_abbreviations"

  so this patch subject becomes:
  "net/bnx2x: set cache line based on build configuration"

- Rx/Tx should not be used as "RX" or "rx" in patch title


- There are three checkpatch warnings of same type on patch 10/10:

CHECK:SPACING: No space is necessary after a cast
#105: FILE: drivers/net/bnx2x/bnx2x.h:1461:
+                         ((uintptr_t) sc->bar[BAR0].base_addr + offset)));

- Is ack from Harish for this patch only or for all patchset? Since this
patchset doesn't have a cover letter, if ack is for patchset please put
Acked-by line to each patch.

Thanks,
ferruh
diff mbox

Patch

diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 78757a8..ed7c55f 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -304,10 +304,7 @@  struct bnx2x_device_type {
 /* TCP with Timestamp Option (32) + IPv6 (40) */
 
 /* max supported alignment is 256 (8 shift) */
-#define BNX2X_RX_ALIGN_SHIFT 8
-/* FW uses 2 cache lines alignment for start packet and size  */
-#define BNX2X_FW_RX_ALIGN_START (1 << BNX2X_RX_ALIGN_SHIFT)
-#define BNX2X_FW_RX_ALIGN_END   (1 << BNX2X_RX_ALIGN_SHIFT)
+#define BNX2X_RX_ALIGN_SHIFT	RTE_MAX(6, min(8, RTE_CACHE_LINE_SIZE_LOG2))
 
 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)