From patchwork Thu Sep 29 10:20:49 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chas Williams <3chas3@gmail.com> X-Patchwork-Id: 16220 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 592E46A95; Thu, 29 Sep 2016 12:21:18 +0200 (CEST) Received: from mail-yb0-f193.google.com (mail-yb0-f193.google.com [209.85.213.193]) by dpdk.org (Postfix) with ESMTP id EE57D591F for ; Thu, 29 Sep 2016 12:21:06 +0200 (CEST) Received: by mail-yb0-f193.google.com with SMTP id t5so792651yba.3 for ; Thu, 29 Sep 2016 03:21:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fPtiMVWvk4D4t70q2f/epsHWCs+PzN8CDRSe4WGID1Y=; b=fvbtpxXcAZ/wgiQXEg5RgPUal+HUT3dS4l/7mqZ+gyMsRiSsZobR0kB18YOoAABq1s fc36u+M2puXKWsYFCNK18K1fxmpao2Irijn9WHC2B4nbqAc9fxJwEf7aBQ/WvkjfYjVt a0pkuU0jSBPS1D7gnfdE1oN5jyjSCOor3E+PkOU8jM4ieixy49KadCxkmq0CJbQMBRUs Z2w2mv6KNP9sA7WzCwubXr0ekWAPsSgcBekJk7W7FvQOnK2ZTr63/v1ELXRxv2RfZii3 AEUTxy8g7PmTVfiwX4avtsUb9znRnY+2+7/Wvg8Spm8JR7iM0Kp9aeeMh+pJqvf6EIyN BrEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fPtiMVWvk4D4t70q2f/epsHWCs+PzN8CDRSe4WGID1Y=; b=klKn9UJaTa6t4vFs4f2NsYgAmfuRq1Qft3xTR346bU/cnvoeX+Aa5UTdvZmsTTk1tr aPdhsoLxTe7Dvy01s16eRZcuorxB4y2EQuLhYGyqBBv1iiCl/w2xpHt47jT8OMjG8iQB r9HNR54rdzH56xVnneppDooHv7o6Pyxgn3FsMI9Gmx62TEs5UQJ2FBs8BE/N9D7xE/tG KJEFXdqN5GIp4jbaImA7gqngzeP8gVGk9YnGMyZ6+q6B2M+hAjyxdv6FyGdQBPpyCSjp uetVuudRyPWXAA3RvHB9pF/aT4X/zOAEJsvyvY0qpC38SSPG/BLpBlXIc5ouSFtYL37w ksoQ== X-Gm-Message-State: AA6/9Rm3r/SLqhGVr7bw85BMmIrqar3b1idSq3MpwjYClfDiTuAeUEC/UN9U91Y0om9PZA== X-Received: by 10.37.112.213 with SMTP id l204mr367053ybc.124.1475144466443; Thu, 29 Sep 2016 03:21:06 -0700 (PDT) Received: from monolith.home (pool-96-231-205-104.washdc.fios.verizon.net. [96.231.205.104]) by smtp.gmail.com with ESMTPSA id z133sm5302430ywb.51.2016.09.29.03.21.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Sep 2016 03:21:06 -0700 (PDT) From: Chas Williams <3chas3@gmail.com> To: dev@dpdk.org Cc: harish.patil@qlogic.com, Chas Williams <3chas3@gmail.com> Date: Thu, 29 Sep 2016 06:20:49 -0400 Message-Id: <1475144449-22176-10-git-send-email-3chas3@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1475144449-22176-1-git-send-email-3chas3@gmail.com> References: <1475144449-22176-1-git-send-email-3chas3@gmail.com> Subject: [dpdk-dev] [PATCH v2 10/10] bnx2x: Merge debug register operations into headers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The register read/writes should just be static inline instead of alternately defined as routines or macros depending on the status of debugging. Fix bnx2x_reg_read32() returning 0 during debug unaligned reads. Fixes: b5bf7719221d ("bnx2x: driver support routines") Signed-off-by: Chas Williams <3chas3@gmail.com> Acked-by: Harish Patil --- drivers/net/bnx2x/Makefile | 1 - drivers/net/bnx2x/bnx2x.h | 99 +++++++++++++++++++++++++++++++++++++--------- drivers/net/bnx2x/debug.c | 96 -------------------------------------------- 3 files changed, 80 insertions(+), 116 deletions(-) delete mode 100644 drivers/net/bnx2x/debug.c diff --git a/drivers/net/bnx2x/Makefile b/drivers/net/bnx2x/Makefile index ab69680..e971fb6 100644 --- a/drivers/net/bnx2x/Makefile +++ b/drivers/net/bnx2x/Makefile @@ -28,7 +28,6 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_ethdev.c SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += ecore_sp.c SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += elink.c SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += bnx2x_vfpf.c -SRCS-$(CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC) += debug.c # this lib depends upon: DEPDIRS-$(CONFIG_RTE_LIBRTE_BNX2X_PMD) += lib/librte_eal lib/librte_ether diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index e4979ac..d1dd6aa 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h @@ -1414,34 +1414,95 @@ struct bnx2x_func_init_params { #define BAR1 2 #define BAR2 4 +static inline void +bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val) +{ + PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", + (unsigned long)offset, val); + *((volatile uint8_t*) + ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; +} + +static inline void +bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val) +{ +#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC + if ((offset % 2) != 0) + PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx", + (unsigned long)offset); +#endif + PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x", + (unsigned long)offset, val); + *((volatile uint16_t*) + ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; +} + +static inline void +bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val) +{ #ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC -uint8_t bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset); -uint16_t bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset); -uint32_t bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset); + if ((offset % 4) != 0) + PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx", + (unsigned long)offset); +#endif -void bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val); -void bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val); -void bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val); -#else -#define bnx2x_reg_write8(sc, offset, val)\ - *((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val + PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + (unsigned long)offset, val); + *((volatile uint32_t*) + ((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; +} + +static inline uint8_t +bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset) +{ + uint8_t val; + + val = (uint8_t)(*((volatile uint8_t*) + ((uintptr_t) sc->bar[BAR0].base_addr + offset))); + PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", + (unsigned long)offset, val); + + return val; +} + +static inline uint16_t +bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset) +{ + uint16_t val; -#define bnx2x_reg_write16(sc, offset, val)\ - *((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val +#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC + if ((offset % 2) != 0) + PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx", + (unsigned long)offset); +#endif -#define bnx2x_reg_write32(sc, offset, val)\ - *((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val + val = (uint16_t)(*((volatile uint16_t*) + ((uintptr_t) sc->bar[BAR0].base_addr + offset))); + PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + (unsigned long)offset, val); -#define bnx2x_reg_read8(sc, offset)\ - (*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))) + return val; +} -#define bnx2x_reg_read16(sc, offset)\ - (*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))) +static inline uint32_t +bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) +{ + uint32_t val; -#define bnx2x_reg_read32(sc, offset)\ - (*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))) +#ifdef RTE_LIBRTE_BNX2X_DEBUG_PERIODIC + if ((offset % 4) != 0) + PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx", + (unsigned long)offset); #endif + val = (uint32_t)(*((volatile uint32_t*) + ((uintptr_t) sc->bar[BAR0].base_addr + offset))); + PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", + (unsigned long)offset, val); + + return val; +} + #define REG_ADDR(sc, offset) (((uint64_t)sc->bar[BAR0].base_addr) + (offset)) #define REG_RD8(sc, offset) bnx2x_reg_read8(sc, (offset)) diff --git a/drivers/net/bnx2x/debug.c b/drivers/net/bnx2x/debug.c deleted file mode 100644 index cc50845..0000000 --- a/drivers/net/bnx2x/debug.c +++ /dev/null @@ -1,96 +0,0 @@ -/*- - * Copyright (c) 2007-2013 QLogic Corporation. All rights reserved. - * - * Eric Davis - * David Christensen - * Gary Zambrano - * - * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. - * Copyright (c) 2015 QLogic Corporation. - * All rights reserved. - * www.qlogic.com - * - * See LICENSE.bnx2x_pmd for copyright and licensing details. - */ - -#include "bnx2x.h" - - -/* - * Debug versions of the 8/16/32 bit OS register read/write functions to - * capture/display values read/written from/to the controller. - */ -void -bnx2x_reg_write8(struct bnx2x_softc *sc, size_t offset, uint8_t val) -{ - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); - *((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; -} - -void -bnx2x_reg_write16(struct bnx2x_softc *sc, size_t offset, uint16_t val) -{ - if ((offset % 2) != 0) { - PMD_DRV_LOG(NOTICE, "Unaligned 16-bit write to 0x%08lx", - (unsigned long)offset); - } - - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%04x", (unsigned long)offset, val); - *((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; -} - -void -bnx2x_reg_write32(struct bnx2x_softc *sc, size_t offset, uint32_t val) -{ - if ((offset % 4) != 0) { - PMD_DRV_LOG(NOTICE, "Unaligned 32-bit write to 0x%08lx", - (unsigned long)offset); - } - - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); - *((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset)) = val; -} - -uint8_t -bnx2x_reg_read8(struct bnx2x_softc *sc, size_t offset) -{ - uint8_t val; - - val = (uint8_t)(*((volatile uint8_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%02x", (unsigned long)offset, val); - - return val; -} - -uint16_t -bnx2x_reg_read16(struct bnx2x_softc *sc, size_t offset) -{ - uint16_t val; - - if ((offset % 2) != 0) { - PMD_DRV_LOG(NOTICE, "Unaligned 16-bit read from 0x%08lx", - (unsigned long)offset); - } - - val = (uint16_t)(*((volatile uint16_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); - - return val; -} - -uint32_t -bnx2x_reg_read32(struct bnx2x_softc *sc, size_t offset) -{ - uint32_t val; - - if ((offset % 4) != 0) { - PMD_DRV_LOG(NOTICE, "Unaligned 32-bit read from 0x%08lx", - (unsigned long)offset); - return 0; - } - - val = (uint32_t)(*((volatile uint32_t*)((uintptr_t)sc->bar[BAR0].base_addr + offset))); - PMD_DEBUG_PERIODIC_LOG(DEBUG, "offset=0x%08lx val=0x%08x", (unsigned long)offset, val); - - return val; -}