From patchwork Wed Dec 14 01:55:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob X-Patchwork-Id: 17935 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 71C0D58CB; Wed, 14 Dec 2016 02:59:04 +0100 (CET) Received: from NAM03-DM3-obe.outbound.protection.outlook.com (mail-dm3nam03on0064.outbound.protection.outlook.com [104.47.41.64]) by dpdk.org (Postfix) with ESMTP id CE04B3989 for ; Wed, 14 Dec 2016 02:58:45 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=BmYWjwpw/DWcxuAoZCuAPCUeQ0sdhpfAoPUTPzkARzg=; b=SCXENsu7fOAn6D6du59ofoXltLiuYKj7r/WTAMNf87bbHKR5Q/uQtXlWgkIXTQ/BxBET//+D02+HBBp9gMWckYUaPHeGf4qOrh0fz+/ZKT76VpGzs9Goko0dFAQR/xrLiIAUFBCfip85+thY8DJUrwxCevXPQiFlH52w+K7cduA= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.Jacob@cavium.com; Received: from localhost.localdomain.localdomain (122.166.91.229) by BN3PR0701MB1719.namprd07.prod.outlook.com (10.163.39.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.771.8; Wed, 14 Dec 2016 01:57:58 +0000 From: Jerin Jacob To: CC: , , , , , Jerin Jacob Date: Wed, 14 Dec 2016 07:25:40 +0530 Message-ID: <1481680558-4003-11-git-send-email-jerin.jacob@caviumnetworks.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com> References: <1481680558-4003-1-git-send-email-jerin.jacob@caviumnetworks.com> MIME-Version: 1.0 X-Originating-IP: [122.166.91.229] X-ClientProxiedBy: MAXPR01CA0006.INDPRD01.PROD.OUTLOOK.COM (10.164.147.13) To BN3PR0701MB1719.namprd07.prod.outlook.com (10.163.39.18) X-MS-Office365-Filtering-Correlation-Id: b34b8bbb-01fb-49fe-2bc8-08d423c4a27c X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:BN3PR0701MB1719; X-Microsoft-Exchange-Diagnostics: 1; BN3PR0701MB1719; 3:2vpvMXTaqYtfS+S3YuWL8X6yptsFxnB9vXJwzSEJloTktXrGMXw6TPpWKN5MTQNZ81dnQ9xQ2DClu711t/GtW7XBao+sUW2p7KVC4PzgOPVvGsO4Kar4VvPM0nhuFDdVRFrzLFgYRPyFoQ+ubLOR5Ub2K3oTo4LfEO9SUQP4P92JpRgCKsfd27CyUy/FIInAiZnp33XfFrM7T1/iniBGo5MyuI/0ZVrxngEhUfO6PLbfXNJA3wOXzjyN+rfxZRZFlfS7gFrtC/vc2crfgRPnMA== X-Microsoft-Exchange-Diagnostics: 1; BN3PR0701MB1719; 25:o0wiSwLr+//hy0gyBKWn932s+ou/BvsoHQycPCSgm5DYf+XpvgubaeWiEX622hUSVBdDjvvW41H+R56IHacyeHElyq66gemv3l2IdnEBgb6buHjR5cj/Un3wT0PAK6ZEPMAbFO8oOvzAfZP2qV7KO8Bw7zfKPzIjXcONS7pI3DCg2ffl1dCMULeeIy8xjLGdx3jaGjFvqG8Dn5R0IZJLZx1aztDuWRfhn9XKkdbFTbeMb2xU06IXP8R0hkdemrEzDgC2Hj4I0uzoH0ZnvTJYfY1zV7bZ8aCaMeXwDA05PmYzkDiazdG21vtbawUHhHIDYeX56gJNi8aaAVJNHwtRD01t9LQOxb9rCNUOZhgkeXqYWkF/QbJaRg0LLO3zfZqo4u6VjWidA/23gyDIWCZdewC8y9rvdtgmukRJwBsJ9jcaBgcCWrn77vR/BXsv2IQJllctJLdRFEbYDhKV3RJtP0Va+0CacatLavxvsxT0KpZoB8fff/waXnP/slVtVSWip4/BD4c+dGenWK4J553BpTM4hYzw3iozX5jvd6rDqozErJW6TtKqa97/jWKCJe7rLeIe7J7Vy+4zj6GJ090ePbSsI7qmRwB3tUDjuF9LpkgAZ4TkCsh0KViWghW4eF78z/Gq4HY8EjYDf4y2lUIECzgOXxzSfxd3tkzj1EulgnIelqAnuzQLTqbzPU7CMgEDYKaOEnPACymh6dFaKAp13Wms67DUnbafdMGTLpYBLlGlspAr4EZh7roUKOjng38wKz4d3CWBNE1LgkMe4z4iIzaJsuZ2rr8V9oUw66sL1huyeY7ezMiV9qj3CXnQi7he X-Microsoft-Exchange-Diagnostics: 1; BN3PR0701MB1719; 31:r9M8zTkoyK+1gzjHxahFZScHc+FW28u93jOXQQFLI6ScEbuy4nigsaMS6B0XTjpFb5lJj2wulA+a0oNK0d+gXdP+Gl9/4R9c2sJVHWWd3eacDwp8LHGdckBIY6zou34/PD52pS0N+TyT81geD7seaqW+bE4bC2hXjmTSo78zdnOZMhmpeCoS9JpcpK6Fn/mZW9FZSXf0MbXmeMSAU0g4V7iydnMuPRywF8p33ZXbrLzE8A6wTTMuon2kCNhxxDsrvEJLGfcqsmfekLio/+vzow==; 20:lQdGu9wWLjqE1ekH3i8kAajwr76RkRpwHX6x6WlEEO1tWnVb8d/r5ckb2286Vhb9Fueujo1M0eQLUSX0n5qbM9mJIhHRxIhPF1oAeEA1uvn0XCB77jzNYFB6DSYEWXI61qVHTropMSAdKs3s4oyYETt7tHwmxewNMVQZi5Djg9M2yQ2qtL8wws7fbFWfjVNtj2Wq4JwW3ejwfCGr/mhkrreDcPF9IoSkWqdOYdXlPesLjSlwePyYddM+4cncVxN4aES0hxhXiK80dV32xtCo7FqJew+FZk7PRVxP9mkfi3pCCWMP2zbf0MkP7BlJJ/VK3Qi8DYZTg2zDjCPKpPsTxgH07ibYMJNBTwPieNhoL8KNyOe+2oj4Qf1IlRp1lsDvIU8AbwAFpdYCOseY0iF859UMQFQ95JcvfHP4wxrCpMi11gUkGglB5RhwV+yFdy1/MEd0g4M0XSB1QYvwxbl6nVdmyW5OW2EP4RVtC9E7/DNuwFV1AAm01a2R8Rbw/WCPBckN6B6AxETYirV+fnDpmpnIyiRFZuJE+2jUeBBfTpTKiw43Wc1fY7uq0QTvCv9DkUbL8M9nsh31MBbnm6T5Py6r6+UOd51gaELlCH7Hdtg= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6040375)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(6041248)(20161123555025)(20161123560025)(20161123562025)(20161123564025)(6072148); SRVR:BN3PR0701MB1719; BCL:0; PCL:0; RULEID:; SRVR:BN3PR0701MB1719; X-Microsoft-Exchange-Diagnostics: 1; BN3PR0701MB1719; 4:9XOpyhEA8nrUz6d7WrHkKqa2QqSANBOSU/rzWopDzh+feuKpOu0FIFIsh1bGOKxFYM4vvhfqqViZifKni6ZgbJHmFqRiWzTjrlYrOrETlAlUTO++XTiIiczf2fYc9o0OAUg3nfelPEQoUqeYDcASnHYWMgMB7dDG0ntRz7HXSBRrLNkZzY7n/R00+BmzDjS7RM1o0p4Xv5hHzZQiCvhOfz/H5haDhwBI/PTcOtLpDKZeCPyHPtP4v2JjhwlfLBDpQHkjXwVtzAXO/ef3uAoEN0tpGwXzv1od3KbNg3TKYuSxvmQwkKW5wd27wdNE1fAhBKFTq+c6vSbc65mxsiFvdlzFLYa4fZNGFT2oak4tVXoeHBdlO3sPIHDLxFB/OiTQk/m//ZzRLj2qwAH9B9yP+XSTgRT8MZ/86Ujbg7l/fvD3iG6a+wghKtdpBeVtHuSg+C1/6XrwwR0ncXkBC/60cfMqOPEtHgfpbkIOFcyDhNmnNe/MdbmEmKJt9wX3UnUuCNJ2GU70DuDgr4SXhHOQyogv8ldKQKDlz8u0ssJj7eADgVHvIp9U+0ua7Mqyh9EV3rj1a93luBd3znJXHB8HtQ== X-Forefront-PRVS: 01565FED4C X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4630300001)(6009001)(6069001)(7916002)(39450400003)(39840400002)(39410400002)(189002)(199003)(6116002)(6512006)(6506006)(6486002)(3846002)(66066001)(68736007)(47776003)(92566002)(5003940100001)(50986999)(76176999)(81156014)(50226002)(2906002)(110136003)(33646002)(6916009)(101416001)(42882006)(2950100002)(6666003)(4326007)(4001430100002)(81166006)(38730400001)(105586002)(8676002)(106356001)(5660300001)(107886002)(305945005)(48376002)(97736004)(50466002)(36756003)(2351001)(42186005)(7736002)(189998001); DIR:OUT; SFP:1101; SCL:1; SRVR:BN3PR0701MB1719; H:localhost.localdomain.localdomain; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; Received-SPF: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; BN3PR0701MB1719; 23:nfO8sR/TkLLAF1LOmAFif2N6XqnFOHUAgm32XHt?= NBAGvVxS5+muIRd6pAPn2y8+ctk098RMkpnndjkXZ2uW5fr+Cd8Wm3gzaqHC7kOUPxZG+qEjBmE4r41qAarBit+QP5q6p3F5poE1ltKz7ucAhhmVQgeaYmPv5a73s5IkE4eJ6pARyg3UxkTQW1tJGR/IfcpOXNOQ/ieXK18gZA2e5ePONEihJsfTmfEIwSaXhhGtnkmOLKeDhyA5rqzjAfizS27x9vKRzzOth1GA5NOoFNoQqbBabrm7nOL2+TUEWO6Os4Qrk72OhJr9uZzg/zkRuZ3clp+jVXnUDUMGpYXoXjedWDeVxS/IDQ2o6Mk7dzDRo2/BtND9/mImCZjrk+YGvEgWyE7xPvsVa3W3zF0Q9aC/rUNf7tHptJUxrUFxu5iD4igxpG5+Bq4ZKbtA5QdmAUJVILfAliamv+idoRonNCpiyjJ1uH/qEA0NFpImjuHO92TbXPTwl4vRGnMSMjZDQRack4Z0Gf9RVQRpLh0rULOGABBVsD8VeFqluUh2z7HqXhr2oOEDn5awHvq5I167lKiVZ61jNFPgkA5c6DNc8WN5I2zz7esXkshH6DQhGvVoJHrmiRiEk6PvFvw+QsKNL7U8rROgh+Di/SzasuscHGU5ghEwbcQQ5QQrXbPlljDbYrtT7wSxkLhIre+Cb7rXxgWNartI83OfsT9zoxNkWTaVo5TiOVVL1YCu7w2WyWQ/I9N4Wnitd53c3DPWgRPbfoPo7Uau15vju/orebHYUf4NRhZDYctOuZVdSBjCjwZNBMJ6IJ57kvn34/0xD8RJOHfbIrZAwys3lHrkHJhA4BZinneN+8U+ZIbgone0wKrQe/AKkGzauQHUHcQlPlowtdw/CcDn3qCZG1Pj14xXlPOIsL8PMf6VHcMzmydkYCYxyt2d2VGruCJ5NA6p0/rXHiLhzuiPVUvnlDyY9puPFRNGrGWuHIgJAZwLNAaQ1bmCElDePku+fSMcz14bGQv+q7R6mKX/o0CJ9cgcQxVF/1yDiaoZrzTmnKo3+fFxgMNc3O/Zwfs5WirFg0gJK3krVH34WYN7MlC7tvutXUv76LKEoKd2qTzxGlJDXfMgu2Q+8Z3hEB3NzWgXJz+/1U1n5Z9A4UlY+ZGOUqa0AfEGa9Q5sQ4FCSgkcKiSYQGW0aFo8j/MTeVpshzZakictOLx+ X-Microsoft-Exchange-Diagnostics: 1; BN3PR0701MB1719; 6:hNBrPzTfi52lZcseEywx9zJl2a3Osi5ekoZFI8P0G8E37Rg4EYdYw5bTHcZcIM0FcvsReUbo9h0ZpC6xI1p/D02go/+2TjXJCLTmj0N6n8lzUskXMhqcsmjXsXsgqN7NNEcHBVY8T+2pVp+8haw/YZQFrTQNcV0bxUNzuOHae6U2EvSfg2ps+6VzAS/jp0e2EOFIePRWWiDzyabjFnrxBD6ZA7hcb45WGJnJ3y1Ccb7QKwPeshe7xRMFDZiHmQag9iKrV5RKWZFmEO4DIQsNCIFwwTcIVdL7HQ3FTsxWy+qnxRSdkvqcSw/qlJ8Kv2Z3n+XA+ISd1vtL6BsoR/vgbyLbNDUjik9EtuZTosGm8oQaUdLnzgtvJA4OYUGg/2YRgQvuw7laav1rl4dSpH/zlAvgfdTYx83Ri1kGjcavhTs=; 5:PRFTbwnG0fv5pUUSfsFybNODeqpHyV+cCecaIMYGAgOh/claF0YHbi8tJJh0HETt2DyGVkq69P71GsVHSFuzFQz+085B7iF7yD+VVG5rhwwolIbq7aHT+TUhofIjn3lbL0GGMby28cBmFDp+sjb3hg==; 24:w6Y6x1S9RSgmdGFad1VTFGCfKj2Mz78Aswd+Kgg5s9WbiL5v/nvcNP9UodezpxR/FUrRJ4hnai6K1jTOgF7gtqc2WxoPtipW0WhYQ7vhUEs= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; BN3PR0701MB1719; 7:lHbQKbFuWVccJVqCaWg/o3yD9jeUAUjmkC/wiG/aRVPVWmrFbTK1vTiRo6VxqRIBKKvWoYc/D2pXAXMWZZHUJu+iuGsFlgd8Dw8bz4MMXg0ZxHkxrObWCsZpmKAthEMEPn1uK7HD0JTWviRmZ880MiCe8bsRR4i3JkYWzdF/6UlleN8FvsRJR2o0T3SmrblqnmRADSLIyjUincg7kTgRd7ijiFTO+uPQf0tGMlQoK9V46Fj9XIfeVnzOPzuI4c2dZZ9jl+OkgSWanGEcFF9N+ChtOqCn/ABW1sdKHxAmn0Nr9DlSKX+asVbtxEmCrS/+NEXTT5UCl2JiGyJRkibtG+lLGmrh3t6qKhbOa2BbY9xeo1/C0d5wV4059ixn0VsEC4wb3K6psJWas/4Me2TlkCDKwcM6pSdRaPoTfesWqtn20y0lhuwL8PFKXJNOcaLK0EnwnqqUJUW09XqRsedR6Q== X-OriginatorOrg: caviumnetworks.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Dec 2016 01:57:58.7220 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR0701MB1719 Subject: [dpdk-dev] [PATCH 10/28] eal: introduce I/O device memory read/write operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit introduces 8-bit, 16-bit, 32bit, 64bit I/O device memory read/write operations along with the relaxed versions. The weakly-ordered machine like ARM needs additional I/O barrier for device memory read/write access over PCI bus. By introducing the eal abstraction for I/O device memory read/write access, The drivers can access I/O device memory in architecture agnostic manner. The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access. Signed-off-by: Jerin Jacob --- doc/api/doxy-api-index.md | 3 +- lib/librte_eal/common/Makefile | 3 +- lib/librte_eal/common/include/generic/rte_io.h | 263 +++++++++++++++++++++++++ 3 files changed, 267 insertions(+), 2 deletions(-) create mode 100644 lib/librte_eal/common/include/generic/rte_io.h diff --git a/doc/api/doxy-api-index.md b/doc/api/doxy-api-index.md index 02d3a46..0ad3367 100644 --- a/doc/api/doxy-api-index.md +++ b/doc/api/doxy-api-index.md @@ -68,7 +68,8 @@ There are many libraries, so their headers may be grouped by topics: [branch prediction] (@ref rte_branch_prediction.h), [cache prefetch] (@ref rte_prefetch.h), [byte order] (@ref rte_byteorder.h), - [CPU flags] (@ref rte_cpuflags.h) + [CPU flags] (@ref rte_cpuflags.h), + [I/O access] (@ref rte_io.h) - **CPU multicore**: [interrupts] (@ref rte_interrupts.h), diff --git a/lib/librte_eal/common/Makefile b/lib/librte_eal/common/Makefile index a92c984..6498c15 100644 --- a/lib/librte_eal/common/Makefile +++ b/lib/librte_eal/common/Makefile @@ -43,7 +43,8 @@ INC += rte_pci_dev_feature_defs.h rte_pci_dev_features.h INC += rte_malloc.h rte_keepalive.h rte_time.h GENERIC_INC := rte_atomic.h rte_byteorder.h rte_cycles.h rte_prefetch.h -GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h +GENERIC_INC += rte_spinlock.h rte_memcpy.h rte_cpuflags.h rte_rwlock.h rte_io.h + # defined in mk/arch/$(RTE_ARCH)/rte.vars.mk ARCH_DIR ?= $(RTE_ARCH) ARCH_INC := $(notdir $(wildcard $(RTE_SDK)/lib/librte_eal/common/include/arch/$(ARCH_DIR)/*.h)) diff --git a/lib/librte_eal/common/include/generic/rte_io.h b/lib/librte_eal/common/include/generic/rte_io.h new file mode 100644 index 0000000..d7ffbcd --- /dev/null +++ b/lib/librte_eal/common/include/generic/rte_io.h @@ -0,0 +1,263 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Cavium networks. All rights reserved. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Cavium networks nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTE_IO_H_ +#define _RTE_IO_H_ + +/** + * @file + * I/O device memory operations + * + * This file defines the generic API for I/O device memory read/write operations + */ + +#include +#include +#include + +#ifdef __DOXYGEN__ + +/** + * Read a 8-bit value from I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint8_t +rte_readb_relaxed(const volatile void *addr); + +/** + * Read a 16-bit value from I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint16_t +rte_readw_relaxed(const volatile void *addr); + +/** + * Read a 32-bit value from I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint32_t +rte_readl_relaxed(const volatile void *addr); + +/** + * Read a 64-bit value from I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint64_t +rte_readq_relaxed(const volatile void *addr); + +/** + * Write a 8-bit value to I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ + +static inline void +rte_writeb_relaxed(uint8_t value, volatile void *addr); + +/** + * Write a 16-bit value to I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_writew_relaxed(uint16_t value, volatile void *addr); + +/** + * Write a 32-bit value to I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_writel_relaxed(uint32_t value, volatile void *addr); + +/** + * Write a 64-bit value to I/O device memory address *addr*. + * + * The relaxed version does not have additional I/O memory barrier, useful in + * accessing the device registers of integrated controllers which implicitly + * strongly ordered with respect to memory access. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_writeq_relaxed(uint64_t value, volatile void *addr); + +/** + * Read a 8-bit value from I/O device memory address *addr*. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint8_t +rte_readb(const volatile void *addr); + +/** + * Read a 16-bit value from I/O device memory address *addr*. + * + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint16_t +rte_readw(const volatile void *addr); + +/** + * Read a 32-bit value from I/O device memory address *addr*. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint32_t +rte_readl(const volatile void *addr); + +/** + * Read a 64-bit value from I/O device memory address *addr*. + * + * @param addr + * I/O memory address to read the value from + * @return + * read value + */ +static inline uint64_t +rte_readq(const volatile void *addr); + +/** + * Write a 8-bit value to I/O device memory address *addr*. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ + +static inline void +rte_writeb(uint8_t value, volatile void *addr); + +/** + * Write a 16-bit value to I/O device memory address *addr*. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_writew(uint16_t value, volatile void *addr); + +/** + * Write a 32-bit value to I/O device memory address *addr*. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_writel(uint32_t value, volatile void *addr); + +/** + * Write a 64-bit value to I/O device memory address *addr*. + * + * @param value + * Value to write + * @param addr + * I/O memory address to write the value to + */ +static inline void +rte_writeq(uint64_t value, volatile void *addr); + +#endif /* __DOXYGEN__ */ + +#endif /* _RTE_IO_H_ */