diff mbox

[dpdk-dev,v2,14/29] eal/arm64: change barrier definitions to macros

Message ID 1482832175-27199-15-git-send-email-jerin.jacob@caviumnetworks.com (mailing list archive)
State Superseded, archived
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel compilation success Compilation OK

Commit Message

Jerin Jacob Dec. 27, 2016, 9:49 a.m. UTC 
  Change rte_?wb definitions to macros in order to
keep consistent with other barrier definitions in
the file.

Suggested-by: Jianbo Liu <jianbo.liu@linaro.org>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
 .../common/include/arch/arm/rte_atomic_64.h        | 36 ++--------------------
 1 file changed, 3 insertions(+), 33 deletions(-)

Comments

Jianbo Liu Jan. 3, 2017, 7:55 a.m. UTC | #1 
On 27 December 2016 at 17:49, Jerin Jacob
<jerin.jacob@caviumnetworks.com> wrote:
> Change rte_?wb definitions to macros in order to

use rte_*mb?

> keep consistent with other barrier definitions in
> the file.
>
> Suggested-by: Jianbo Liu <jianbo.liu@linaro.org>
> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> ---
>  .../common/include/arch/arm/rte_atomic_64.h        | 36 ++--------------------
>  1 file changed, 3 insertions(+), 33 deletions(-)
>
> diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> index ef0efc7..dc3a0f3 100644
> --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> @@ -46,41 +46,11 @@ extern "C" {
>  #define dsb(opt)  { asm volatile("dsb " #opt : : : "memory"); }
>  #define dmb(opt)  { asm volatile("dmb " #opt : : : "memory"); }
>
> -/**
> - * General memory barrier.
> - *
> - * Guarantees that the LOAD and STORE operations generated before the
> - * barrier occur before the LOAD and STORE operations generated after.
> - * This function is architecture dependent.
> - */
> -static inline void rte_mb(void)
> -{
> -       dsb(sy);
> -}
> +#define rte_mb() dsb(sy)
>
> -/**
> - * Write memory barrier.
> - *
> - * Guarantees that the STORE operations generated before the barrier
> - * occur before the STORE operations generated after.
> - * This function is architecture dependent.
> - */
> -static inline void rte_wmb(void)
> -{
> -       dsb(st);
> -}
> +#define rte_wmb() dsb(st)
>
> -/**
> - * Read memory barrier.
> - *
> - * Guarantees that the LOAD operations generated before the barrier
> - * occur before the LOAD operations generated after.
> - * This function is architecture dependent.
> - */

How about keep the comments for all these macros?

> -static inline void rte_rmb(void)
> -{
> -       dsb(ld);
> -}
> +#define rte_rmb() dsb(ld)
>
>  #define rte_smp_mb() dmb(ish)
>
> --
> 2.5.5
>
Jerin Jacob Jan. 4, 2017, 10:09 a.m. UTC | #2 
On Tue, Jan 03, 2017 at 03:55:45PM +0800, Jianbo Liu wrote:
> On 27 December 2016 at 17:49, Jerin Jacob
> <jerin.jacob@caviumnetworks.com> wrote:
> > Change rte_?wb definitions to macros in order to
> 
> use rte_*mb?

IMHO, regex ? is appropriate here.
https://en.wikipedia.org/wiki/Regular_expression

> 
> > keep consistent with other barrier definitions in
> > the file.
> >
> > Suggested-by: Jianbo Liu <jianbo.liu@linaro.org>
> > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> > ---
> >  .../common/include/arch/arm/rte_atomic_64.h        | 36 ++--------------------
> >  1 file changed, 3 insertions(+), 33 deletions(-)
> >
> > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > index ef0efc7..dc3a0f3 100644
> > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > @@ -46,41 +46,11 @@ extern "C" {
> >  #define dsb(opt)  { asm volatile("dsb " #opt : : : "memory"); }
> >  #define dmb(opt)  { asm volatile("dmb " #opt : : : "memory"); }
> >
> > -/**
> > - * General memory barrier.
> > - *
> > - * Guarantees that the LOAD and STORE operations generated before the
> > - * barrier occur before the LOAD and STORE operations generated after.
> > - * This function is architecture dependent.
> > - */
> > -static inline void rte_mb(void)
> > -{
> > -       dsb(sy);
> > -}
> > +#define rte_mb() dsb(sy)
> >
> > -/**
> > - * Write memory barrier.
> > - *
> > - * Guarantees that the STORE operations generated before the barrier
> > - * occur before the STORE operations generated after.
> > - * This function is architecture dependent.
> > - */
> > -static inline void rte_wmb(void)
> > -{
> > -       dsb(st);
> > -}
> > +#define rte_wmb() dsb(st)
> >
> > -/**
> > - * Read memory barrier.
> > - *
> > - * Guarantees that the LOAD operations generated before the barrier
> > - * occur before the LOAD operations generated after.
> > - * This function is architecture dependent.
> > - */
> 
> How about keep the comments for all these macros?

lib/librte_eal/common/include/generic/rte_atomic.h file has description
for all the barriers.All other arch are doing in the same-way.

> 
> > -static inline void rte_rmb(void)
> > -{
> > -       dsb(ld);
> > -}
> > +#define rte_rmb() dsb(ld)
> >
> >  #define rte_smp_mb() dmb(ish)
> >
> > --
> > 2.5.5
> >
Tiwei Bie Jan. 4, 2017, 11 a.m. UTC | #3 
On Wed, Jan 04, 2017 at 03:39:14PM +0530, Jerin Jacob wrote:
> On Tue, Jan 03, 2017 at 03:55:45PM +0800, Jianbo Liu wrote:
> > On 27 December 2016 at 17:49, Jerin Jacob
> > <jerin.jacob@caviumnetworks.com> wrote:
> > > Change rte_?wb definitions to macros in order to
> > 
> > use rte_*mb?
> 
> IMHO, regex ? is appropriate here.
> https://en.wikipedia.org/wiki/Regular_expression
> 

The APIs you're changing are:

> +#define rte_mb() dsb(sy)
> +#define rte_wmb() dsb(st)
> +#define rte_rmb() dsb(ld)

If it's a regex, shouldn't it be: rte_[wr]?mb or rte_.?mb

If ? is a wildcard used by shell, it should at least be: rte_?mb
But rte_*mb is easier to recognize, and matches all of them. :-)

Best regards,
Tiwei Bie

> > 
> > > keep consistent with other barrier definitions in
> > > the file.
> > >
> > > Suggested-by: Jianbo Liu <jianbo.liu@linaro.org>
> > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> > > ---
> > >  .../common/include/arch/arm/rte_atomic_64.h        | 36 ++--------------------
> > >  1 file changed, 3 insertions(+), 33 deletions(-)
> > >
> > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > index ef0efc7..dc3a0f3 100644
> > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > @@ -46,41 +46,11 @@ extern "C" {
> > >  #define dsb(opt)  { asm volatile("dsb " #opt : : : "memory"); }
> > >  #define dmb(opt)  { asm volatile("dmb " #opt : : : "memory"); }
> > >
> > > -/**
> > > - * General memory barrier.
> > > - *
> > > - * Guarantees that the LOAD and STORE operations generated before the
> > > - * barrier occur before the LOAD and STORE operations generated after.
> > > - * This function is architecture dependent.
> > > - */
> > > -static inline void rte_mb(void)
> > > -{
> > > -       dsb(sy);
> > > -}
> > > +#define rte_mb() dsb(sy)
> > >
> > > -/**
> > > - * Write memory barrier.
> > > - *
> > > - * Guarantees that the STORE operations generated before the barrier
> > > - * occur before the STORE operations generated after.
> > > - * This function is architecture dependent.
> > > - */
> > > -static inline void rte_wmb(void)
> > > -{
> > > -       dsb(st);
> > > -}
> > > +#define rte_wmb() dsb(st)
> > >
> > > -/**
> > > - * Read memory barrier.
> > > - *
> > > - * Guarantees that the LOAD operations generated before the barrier
> > > - * occur before the LOAD operations generated after.
> > > - * This function is architecture dependent.
> > > - */
> > 
> > How about keep the comments for all these macros?
> 
> lib/librte_eal/common/include/generic/rte_atomic.h file has description
> for all the barriers.All other arch are doing in the same-way.
> 
> > 
> > > -static inline void rte_rmb(void)
> > > -{
> > > -       dsb(ld);
> > > -}
> > > +#define rte_rmb() dsb(ld)
> > >
> > >  #define rte_smp_mb() dmb(ish)
> > >
> > > --
> > > 2.5.5
> > >
Jerin Jacob Jan. 4, 2017, 1:03 p.m. UTC | #4 
On Wed, Jan 04, 2017 at 07:00:30PM +0800, Tiwei Bie wrote:
> On Wed, Jan 04, 2017 at 03:39:14PM +0530, Jerin Jacob wrote:
> > On Tue, Jan 03, 2017 at 03:55:45PM +0800, Jianbo Liu wrote:
> > > On 27 December 2016 at 17:49, Jerin Jacob
> > > <jerin.jacob@caviumnetworks.com> wrote:
> > > > Change rte_?wb definitions to macros in order to
> > > 
> > > use rte_*mb?
> > 
> > IMHO, regex ? is appropriate here.
> > https://en.wikipedia.org/wiki/Regular_expression
> > 
> 
> The APIs you're changing are:
> 
> > +#define rte_mb() dsb(sy)
> > +#define rte_wmb() dsb(st)
> > +#define rte_rmb() dsb(ld)
> 
> If it's a regex, shouldn't it be: rte_[wr]?mb or rte_.?mb
> 
> If ? is a wildcard used by shell, it should at least be: rte_?mb
> But rte_*mb is easier to recognize, and matches all of them. :-)

OK. I will wait for further comments on this patchset(especially comments
on driver changes) and post v3 to fix this

> 
> Best regards,
> Tiwei Bie
> 
> > > 
> > > > keep consistent with other barrier definitions in
> > > > the file.
> > > >
> > > > Suggested-by: Jianbo Liu <jianbo.liu@linaro.org>
> > > > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> > > > ---
> > > >  .../common/include/arch/arm/rte_atomic_64.h        | 36 ++--------------------
> > > >  1 file changed, 3 insertions(+), 33 deletions(-)
> > > >
> > > > diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > > index ef0efc7..dc3a0f3 100644
> > > > --- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > > +++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
> > > > @@ -46,41 +46,11 @@ extern "C" {
> > > >  #define dsb(opt)  { asm volatile("dsb " #opt : : : "memory"); }
> > > >  #define dmb(opt)  { asm volatile("dmb " #opt : : : "memory"); }
> > > >
> > > > -/**
> > > > - * General memory barrier.
> > > > - *
> > > > - * Guarantees that the LOAD and STORE operations generated before the
> > > > - * barrier occur before the LOAD and STORE operations generated after.
> > > > - * This function is architecture dependent.
> > > > - */
> > > > -static inline void rte_mb(void)
> > > > -{
> > > > -       dsb(sy);
> > > > -}
> > > > +#define rte_mb() dsb(sy)
> > > >
> > > > -/**
> > > > - * Write memory barrier.
> > > > - *
> > > > - * Guarantees that the STORE operations generated before the barrier
> > > > - * occur before the STORE operations generated after.
> > > > - * This function is architecture dependent.
> > > > - */
> > > > -static inline void rte_wmb(void)
> > > > -{
> > > > -       dsb(st);
> > > > -}
> > > > +#define rte_wmb() dsb(st)
> > > >
> > > > -/**
> > > > - * Read memory barrier.
> > > > - *
> > > > - * Guarantees that the LOAD operations generated before the barrier
> > > > - * occur before the LOAD operations generated after.
> > > > - * This function is architecture dependent.
> > > > - */
> > > 
> > > How about keep the comments for all these macros?
> > 
> > lib/librte_eal/common/include/generic/rte_atomic.h file has description
> > for all the barriers.All other arch are doing in the same-way.
> > 
> > > 
> > > > -static inline void rte_rmb(void)
> > > > -{
> > > > -       dsb(ld);
> > > > -}
> > > > +#define rte_rmb() dsb(ld)
> > > >
> > > >  #define rte_smp_mb() dmb(ish)
> > > >
> > > > --
> > > > 2.5.5
> > > >
diff mbox

Patch

diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
index ef0efc7..dc3a0f3 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_64.h
@@ -46,41 +46,11 @@  extern "C" {
 #define dsb(opt)  { asm volatile("dsb " #opt : : : "memory"); }
 #define dmb(opt)  { asm volatile("dmb " #opt : : : "memory"); }
 
-/**
- * General memory barrier.
- *
- * Guarantees that the LOAD and STORE operations generated before the
- * barrier occur before the LOAD and STORE operations generated after.
- * This function is architecture dependent.
- */
-static inline void rte_mb(void)
-{
-	dsb(sy);
-}
+#define rte_mb() dsb(sy)
 
-/**
- * Write memory barrier.
- *
- * Guarantees that the STORE operations generated before the barrier
- * occur before the STORE operations generated after.
- * This function is architecture dependent.
- */
-static inline void rte_wmb(void)
-{
-	dsb(st);
-}
+#define rte_wmb() dsb(st)
 
-/**
- * Read memory barrier.
- *
- * Guarantees that the LOAD operations generated before the barrier
- * occur before the LOAD operations generated after.
- * This function is architecture dependent.
- */
-static inline void rte_rmb(void)
-{
-	dsb(ld);
-}
+#define rte_rmb() dsb(ld)
 
 #define rte_smp_mb() dmb(ish)