From patchwork Tue Jan 17 18:52:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 19586 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 796BAFA33; Tue, 17 Jan 2017 14:20:15 +0100 (CET) Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0046.outbound.protection.outlook.com [104.47.33.46]) by dpdk.org (Postfix) with ESMTP id F1903F974 for ; Tue, 17 Jan 2017 14:20:05 +0100 (CET) Received: from BN3PR03CA0099.namprd03.prod.outlook.com (10.174.66.17) by DM2PR0301MB0749.namprd03.prod.outlook.com (10.160.97.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.860.13; Tue, 17 Jan 2017 13:20:04 +0000 Received: from BY2FFO11FD018.protection.gbl (2a01:111:f400:7c0c::127) by BN3PR03CA0099.outlook.office365.com (2603:10b6:400:4::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.860.13 via Frontend Transport; Tue, 17 Jan 2017 13:20:04 +0000 Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; nxp.com; dmarc=fail action=none header.from=nxp.com; nxp.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of nxp.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Received: from tx30smr01.am.freescale.net (192.88.168.50) by BY2FFO11FD018.mail.protection.outlook.com (10.1.14.106) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.803.8 via Frontend Transport; Tue, 17 Jan 2017 13:20:03 +0000 Received: from bf-netperf1.idc ([10.232.134.28]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id v0HDJ8mM021741; Tue, 17 Jan 2017 06:20:00 -0700 From: Hemant Agrawal To: CC: , , , , , , Hemant Agrawal Date: Wed, 18 Jan 2017 00:22:36 +0530 Message-ID: <1484679174-4174-16-git-send-email-hemant.agrawal@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1484679174-4174-1-git-send-email-hemant.agrawal@nxp.com> References: <1482988612-6638-1-git-send-email-shreyansh.jain@nxp.com> <1484679174-4174-1-git-send-email-hemant.agrawal@nxp.com> X-EOPAttributedMessage: 0 X-Matching-Connectors: 131291328034989484; (91ab9b29-cfa4-454e-5278-08d120cd25b8); () X-Forefront-Antispam-Report: CIP:192.88.168.50; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(336005)(7916002)(39840400002)(39850400002)(39410400002)(39400400002)(39380400002)(39450400003)(39860400002)(2980300002)(1109001)(1110001)(339900001)(199003)(189002)(36756003)(81156014)(50466002)(81166006)(110136003)(97736004)(8676002)(33646002)(104016004)(4326007)(189998001)(48376002)(85426001)(8656002)(54906002)(38730400001)(77096006)(86362001)(2950100002)(6916009)(626004)(8936002)(6666003)(5660300001)(76176999)(2351001)(551934003)(50986999)(356003)(47776003)(5003940100001)(92566002)(106466001)(30001)(68736007)(305945005)(50226002)(105606002)(2906002); DIR:OUT; SFP:1101; SCL:1; SRVR:DM2PR0301MB0749; H:tx30smr01.am.freescale.net; FPR:; SPF:Fail; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD018; 1:B2nQrhpR9mXGAMS3PkIDwP80fUUwAT+zcFcMwkObGPUVmgxg3+Z6tb/5oqh4odBruXK1mG7zc9pJ8JKMss71lIuUFiw+SNEg3yk1aZgGuEluQrIH+JhrpK2TestPHtct2ucl/n6OCR8bf+7iTLDFRl6lSqND2sdxonmbQfeeVJf2w9uhMJbYo8S+Ylc6sU/qaU0adO8Yp4H0EOqY1zLmJwExFc7j58Uz5Boq14DPDVS6vvrcX2ZBm77Lvu9+IHXpWDjKM4xdAuoa0izYf5qU84iGWANUx2As8T6xDNwxewmKhPoqrwa8Igu9C4NAV06fV04FsTMUzzsRm5czZ1dCMFzY04YtVR312xs1WPtS4EoaPN57UVtz+6pPWXmceLl2jV9LCJxE90pwBRoIJD33MvG+c/CvANlIHGlABYdDZOW1aFwnAeHehiWB6+X/Cjyso/nNmwdGVEJv9tIP+1Un3b40WmPaRrw2vxr8MsaKj584t5AOTxG71YBAgYDZL3E4rRri1pRtt041r1lXK51aZIJt8XHdam+l5wQddtHOYEM8QFL35PErqlAntRBA34dbwLvWGTRANull61HHQqmZZcK+OyWdPEPhLXC7PkyNcsJGHaUKS0nPY+rDFg39/KyJFsaZrXRvGLMLg+FrN8YoT8Dz7AnKQuBHbMdkCnx7JXVHUuYR3QHKgCINU19tabRAPq004AjXuHyhbP1TKzYS4cIwvSdjhvss6jAJEGiWqHjw77IegncAgc9FNIZfbYU7 MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 8db5ba1c-8a9e-4fea-65ac-08d43edb8c14 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001); SRVR:DM2PR0301MB0749; X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0749; 3:5MNXT0AAob0KhtK+iWCtjIUoqv1YRcfkOtJNf3BSgOQ1dvLmks95+8fDV/QL/23BjFIYFD+XbcrA9UwcQ8U61YgcHamo3yN7cazWAdMXHGPwt6ifxXXyehXMQjpjxVNuFk5ylC8ZDoG7+9sA+Szu/Ev5gFETooF2zJcwhyJkYeeVUK1W7Fo5eLm3uI9LAwMwCbAsrwzT3cvb7xV6nnAFqax0B3/aKd9RTfF76mh+Z26BxV+ANRwTOeExr0a10DynY1fNRp/Lcdsytp5AeDyp2uUYx49E9tYV5R2iuKJ681g3QJyKZ0rp7hinyGk1nGfIC+YyGBURT1V7xV4PL6IKHPE0qdNvEfNxagBuRcR7b1i8vnqKk6YkfP59Z+MHCGDR; 25:ghCkZHpUkzkMxthpGqGHRjDv/TH2km4WAng7hSWilzjRwnjfCR714huyEzgjcrdGeUR1G+qnhbJmclLTa+eA48J6DcH+/tB/VQukTmBQXaKMOtRNlcyVck9hzVIBmFGZ3tqqfI3xivHEwhn08jPxdKZoU067NU/R57sJ4qBobd3buW6r1xbSQQVOSQqBWkxLXZq/JKIw5MEqmtX8QlUeOUEuxXK/azuVJf9Thc9UP/l9G7wCjLhci1m0Koh+kZiNSh6Lr53L8iVYYmndYJB63xqhLy34zdLlECT4T050LsBitixmED5QNWwB1+5w3C8Hvbvy6VjhF2mMSsTXqjFssI1jM/kY16hBgo9lhwmwi78hVCr81WJ/mWOGmsj1H1oik3L2EK1RIStdcXSplyE39ma49W8LmVYx0t9Y2vTNZtS7KBcqQkok/Jt3H7Yv87SrCEFGrMkz6DRrlOui5NbUWQ== X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0749; 31:66fOaCKv42RthFI3BpbpRHabE0JYyNwoiMARAJtZmAOF1q8dN1ifveYlF4EBeTcmwYBrzCdqnPYBK36L8Br5yWA8/ZfAHsn55rD3Fa2Siazg8VGtUv+aKyfY2WBhkRVgUTrWyoXDXSmxFGQhRX4NojqNHZE1izdbrEx1Rp2c7QzatcvKOReVV6fTi6MANWngK1BnPtRTnYw5wgX3OSmQmac2cudylNm6P2ncjxNSHf3bICwIyYqzd1gC8r/reqP0P64QjDZzcNTA+EZhdwSbQop9k1qnTfFbOqL6mJAwu8c= X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:(185117386973197)(275809806118684); X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(6095060)(601004)(2401047)(13023025)(13017025)(13015025)(13024025)(13018025)(5005006)(8121501046)(3002001)(10201501046)(6055026)(6096035)(20161123561025)(20161123559025)(20161123556025)(20161123563025)(20161123565025); SRVR:DM2PR0301MB0749; BCL:0; PCL:0; RULEID:(400006); SRVR:DM2PR0301MB0749; X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0749; 4:A2ElUFhmoOSPmkdFiucqWTmSg1mY1Wm/R05YG2XKPjZm8KLtSgYkbX09/cG/jklG8H+8QvBSrTdlUQSQiIXQVAzOWjDavLe8KGzsti/pzwaN2rPaJsfRKjJ6bcjGQuL6av8ri95xwTSB+5M+nPGgi2aLaHdYdUWU3TXJnIW6OTE/Ce4JJLDAV545bxoOT3apPa9mTr8NcHCP9BRhD+IL0OXP94BY1kdB9An1Tbu7zuTSvdxvnOiQ/NySwblVWoLOcLyZVlL0V/D+F1RFs15tDDLEAm8atvmNaddp8U0AcXjwEKYSRW0OyrQubiQU2PgdmU/n2sMhXGhfySuyrAtKFo5obf2UPwJk4iu/zZv0CL0AvH9hFnH8PTw3m1HGEHSQExsQKqODBrTumUhH2d3St/dZrRCQY3CVCc/tJAhmTFxbHuF3eV//FaT0JE2e+bWA/9Et58N+qEwfsgL5/6Q5cr6ntugx9+1Zb2ymCW7Yj19XsH4vytl2e5ZDWuhWwkUk+q+ZY9eVxIxlW9TfKk4a6eqvl1fLgse09rXv7m7mPSlMlKyr/3UayXpZsCOJQRdu1mbn3wKiq4X5lMFK/0SxakZ6j6bEWm5Tb2khJB3uiiaHZgGzl7I1b4a2hHdaixWLosFIin3xYs9kk0sey6Emr6Z5nCu85ASIUAMrtrq9Y23NrNuCO6BN7CibVNG1pSjPxCFY8eSXuW4bEgJRX78STtnqUBT1qzU8Yb3i7jmgwqVxJlCPmwjQP6ZLSgZ72mgTHwgDobA/t+/Gi7EWZdoREg== X-Forefront-PRVS: 01901B3451 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM2PR0301MB0749; 23:7yCigIIrbueXYX1Jyl1va7XzRNp47BiybmFaKvX?= JL1K2TeGpgZx9BfO7JM8YCf/CLeK4X+TI+r2K2qG4kmeEHsDkYKoKjcZdIOyTY7huzEes1Vii0DlW07j6Xn038Pd0vC2/Gtze2oSL51CLksvS/X7mjlQ2xjyQ0MhqtQQY74ZS4M22ak7sLD5mO5Ok5q4W0K8z8X5MminWG0IaxGmo+5p0XZRjE24Jy4FAx6fGZTy9OVwFa/4HYYzJlOrEvvWqny88PnN4Hv28Wh1zmD16mYIaokmo7e3eJmoJpyLNsy+S5ubfv2LnWB6hOi+3ZaJf1ztcecO4zX0Pgg9h8wzl9iliQlKuib2fYM563maMD0iRGC8hQXmEgh6TgDlQIVk78ue0yH0dpohB2Mk+zcsFe+0pRTVSY+/Kvlqi07/6Vs097kFur4LqL3ViOHbD7qcTjMw9OGJbov9ZfXglK1oEaH5coPAz69BaPGZv2FZUZ54Zfn+5AOCeoDewo9V8RHwB0MXwSwKROP0v7pBfjT+rMSL1sxEsIn3WD2e0s2Wj2iOZPHJXGlsGv6AGAKNozumxeil60i7H09t3fMjkLgADuCM4Rc3XVo63BzwDuw0wOTX3WgmXkMk3nqGCLUl2ngqQ1mOPbELc/l5io3mtDFbXovAi7dXwYo2kz5H0q2Iovai9kBTk0MiZy2WryL0JqhnLjztev1yjrsGioeHES7dtRTq3yvTkWjPI2jPlOE/9IbK2vfdrw2Nj0b8p8BbR+bwm/UErWkw576EBBUesYZtakB2Ej+lBnIKiV0ar3HLKchOCO8DOKwpmAdRQFU//qEPPKrelw1F/engyu6T9OMJm26PhqsmnLTUbzNgc1sexH/QSwIslE2x9cTr95+GRkmMHFWyzIWEV6ohbSj6MaLAdK3Z6w/ktc0526VUzERLzRe1vwFTT6zp7VcZX/Tcs91hGz1bLDVBXqsxvG54pv9ohVKOLj0JDKim+BbHXKZBEQwkdLsmCN9WDnooHfZf34GAiERcfMrpByveqwT1X9VLsS0mVX3oVHmav9ragv/pIJ4g2vDN5sbdZ9UjzbWbH9xtk0Wp+0ViVDhm8u21CStepVj9IAImxFE9praGftjegHlZxOlhk9bMm3WhRguItXPJ3OgsceGod6nOvXnbv8uXUxCyLzT8aHWQMHR0nOXUsBOcJC1TXJJMGhXFSvCpS/bDJHZCTYKDBQMceGpKTNq3yJKR5pP5FWYCPfKDApXM2AFZn2K+ipaUsystbgZqB9R3aDE/9PB6m1JJqKy58qtCBI1il8MKaW/OTbdbZzLVP9V2lnGn88Y62LLXBlFxqnmOP X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0749; 6:t7j0NywANxMYCkgVdL30/R/MzGTgkUSISWLHBAVmpZkOKGQrW2JWlzeUlDF/mzieCI7B94yHe7r77IoLB9u1AIPRFI8SZkJMLeJ/XoOYVxYwxYWiAgmroCDKE6v25m1fC5YypQiUx30ft8Gf/bXkQzyf00uz7H3xvghZ4L9AM/FrA/E4VsULkkbp+3L/UWcSyQ1g5el5HdjJbbSrtV17ixocdlANGhP38zKLtk2UhlkphzekAeCb34ce269IqLmrL5x48soHTkNJl2LKH6CjZyrUNj6S6MnzD1deDMTY5ZPkea5LFtJ3GZVm435y3jax463JmF2Cq98GQmUC5jFYRMGs77axVd9BQXYuNPjgT6gifN8bRvjk9+UpQMb0AnLvvuceKk4a4UQBUmpUaNex6x01z5WyaXqucDS13AqtGf/1TCNIhvgHYklZopCHLnr1; 5:xqsoKXkI5GMKadQ/esP6QA6WgOtsFifvT0bHFlqUN1B5wYyL5sx8OHno8uAjL/ArOKGtFZ5mVlY7hhgRUg5lJUJ/LR2rAys/MDfeHldmp1RA6/2oSy6mnpziyY5BX9sI01WoW8CWcU3LPv9z5csGheaixm78GkKz5RRweBJl4NMf0X7v5eX4PME6sk3xPHjq; 24:g+T6tZI8jTaS2Rx4U++4DQjnVSDarmQ+etZ8uc/Quio3CM1uv+rZSpe5gGLqPk+vXkFac9uwGvnitvK0p78g5Cfgv2U5QvzqwSJrRpEmpg0= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM2PR0301MB0749; 7:iKHyAGsY0HOTldoTOKMLikmQQ9DW4ym86amkp61pdzbzyorUk+ctO/txTN5ekWHpIjglA5bs++2DJUFlX/JenKzNu6Cwimz+6tBmuQ131nPGp3RCcjR4f14/HONH6IWTz3A+ZP5/niCcqgAvcFjKebyJIR+jPtxFisgBaXNiVxjFOKEoveB/R40cIFjFjJlm7l7mquKH9yEYD91rdzHnq71ZBoXgF8CezBw2AYR7JiMX2sl7UMGIJOpMLPhXwQ1hkv26KM1mRnGS0nbqJLYzVYN16kXRN4R37OtQIqy15fTL4Wq3QKkgjp/wABevHHDQlKbq+GOjjowBsfVPVdX+GG715QXIzwecKhniVPbBJ74IbAZidZdC7BTxsr1s5q5NWQZp3LDMyww4cHznD7ouc9H9YZcc9snyGh3XKoLoR3KUQkbIKzGZgi9OxayxjNu4vZ3HX0S/ia1OGd1LHiD3sA== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jan 2017 13:20:03.2961 (UTC) X-MS-Exchange-CrossTenant-Id: 5afe0b00-7697-4969-b663-5eab37d5f47e X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0301MB0749 Subject: [dpdk-dev] [PATCHv4 15/33] drivers/common/dpaa2: dpio portal driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The portal driver is bound to DPIO objects discovered on the fsl-mc bus and provides services that: - allow other drivers, such as the Ethernet driver, to enqueue and dequeue frames for their respective objects A system will typically allocate 1 DPIO object per CPU to allow queuing operations to happen simultaneously across all CPUs. Signed-off-by: Hemant Agrawal --- drivers/bus/fslmc/Makefile | 3 + drivers/bus/fslmc/fslmc_vfio.c | 17 +- drivers/bus/fslmc/fslmc_vfio.h | 5 + drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 364 +++++++++++++++++++++++++ drivers/bus/fslmc/portal/dpaa2_hw_dpio.h | 60 ++++ drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 68 +++++ drivers/bus/fslmc/rte_pmd_fslmcbus_version.map | 2 + drivers/common/Makefile | 4 + 8 files changed, 522 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dpio.c create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_dpio.h create mode 100644 drivers/bus/fslmc/portal/dpaa2_hw_pvt.h diff --git a/drivers/bus/fslmc/Makefile b/drivers/bus/fslmc/Makefile index b74c333..1b815dd 100644 --- a/drivers/bus/fslmc/Makefile +++ b/drivers/bus/fslmc/Makefile @@ -46,6 +46,7 @@ CFLAGS += "-Wno-strict-aliasing" CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc CFLAGS += -I$(RTE_SDK)/drivers/bus/fslmc/mc +CFLAGS += -I$(RTE_SDK)/drivers/common/dpaa2/qbman/include CFLAGS += -I$(RTE_SDK)/lib/librte_eal/linuxapp/eal # versioning export map @@ -61,10 +62,12 @@ SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += \ mc/dpio.c \ mc/mc_sys.c +SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += portal/dpaa2_hw_dpio.c SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_vfio.c SRCS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += fslmc_bus.c # library dependencies DEPDIRS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += lib/librte_eal +DEPDIRS-$(CONFIG_RTE_LIBRTE_FSLMC_BUS) += lib/librte_pmd_dpaa2_qbman include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/bus/fslmc/fslmc_vfio.c b/drivers/bus/fslmc/fslmc_vfio.c index fd844e2..8d24620 100644 --- a/drivers/bus/fslmc/fslmc_vfio.c +++ b/drivers/bus/fslmc/fslmc_vfio.c @@ -61,6 +61,9 @@ #include "rte_fslmc.h" #include "fslmc_vfio.h" +#include "portal/dpaa2_hw_pvt.h" +#include "portal/dpaa2_hw_dpio.h" + #define VFIO_MAX_CONTAINERS 1 #define FSLMC_VFIO_LOG(level, fmt, args...) \ @@ -261,12 +264,13 @@ int fslmc_vfio_process_group(void) struct fslmc_vfio_device *vdev; struct vfio_device_info device_info = { .argsz = sizeof(device_info) }; char *temp_obj, *object_type, *mcp_obj, *dev_name; - int32_t object_id, i, dev_fd; + int32_t object_id, i, dev_fd, ret; DIR *d; struct dirent *dir; char path[PATH_MAX]; int64_t v_addr; int ndev_count; + int dpio_count = 0; struct fslmc_vfio_group *group = &vfio_groups[0]; static int process_once; @@ -409,9 +413,20 @@ int fslmc_vfio_process_group(void) fslmc_bus_add_device(dev); } + if (!strcmp(object_type, "dpio")) { + ret = dpaa2_create_dpio_device(vdev, + &device_info, + object_id); + if (!ret) + dpio_count++; + } } closedir(d); + ret = dpaa2_affine_qbman_swp(); + if (ret) + FSLMC_VFIO_LOG(DEBUG, "Error in affining qbman swp %d", ret); + return 0; FAILURE: diff --git a/drivers/bus/fslmc/fslmc_vfio.h b/drivers/bus/fslmc/fslmc_vfio.h index 5e58211..39994dd 100644 --- a/drivers/bus/fslmc/fslmc_vfio.h +++ b/drivers/bus/fslmc/fslmc_vfio.h @@ -71,4 +71,9 @@ int vfio_dmamap_mem_region( int fslmc_vfio_setup_group(void); int fslmc_vfio_process_group(void); +/* create dpio device */ +int dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev, + struct vfio_device_info *obj_info, + int object_id); + #endif /* _FSLMC_VFIO_H_ */ diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c new file mode 100644 index 0000000..011bd9f --- /dev/null +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.c @@ -0,0 +1,364 @@ +/*- + * BSD LICENSE + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (c) 2016 NXP. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Freescale Semiconductor, Inc nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "dpaa2_hw_pvt.h" +#include "dpaa2_hw_dpio.h" + +#define NUM_HOST_CPUS RTE_MAX_LCORE + +struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE]; +RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); + +TAILQ_HEAD(dpio_device_list, dpaa2_dpio_dev); +static struct dpio_device_list *dpio_dev_list; /*!< DPIO device list */ +static uint32_t io_space_count; + +/*Stashing Macros default for LS208x*/ +static int dpaa2_core_cluster_base = 0x04; +static int dpaa2_cluster_sz = 2; + +/* For LS208X platform There are four clusters with following mapping: + * Cluster 1 (ID = x04) : CPU0, CPU1; + * Cluster 2 (ID = x05) : CPU2, CPU3; + * Cluster 3 (ID = x06) : CPU4, CPU5; + * Cluster 4 (ID = x07) : CPU6, CPU7; + */ +/* For LS108X platform There are two clusters with following mapping: + * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3; + * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7; + */ + +/* Set the STASH Destination depending on Current CPU ID. + * e.g. Valid values of SDEST are 4,5,6,7. Where, + * CPU 0-1 will have SDEST 4 + * CPU 2-3 will have SDEST 5.....and so on. + */ +static int +dpaa2_core_cluster_sdest(int cpu_id) +{ + int x = cpu_id / dpaa2_cluster_sz; + + if (x > 3) + x = 3; + + return dpaa2_core_cluster_base + x; +} + +static int +configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev) +{ + struct qbman_swp_desc p_des; + struct dpio_attr attr; + + dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io)); + if (!dpio_dev->dpio) { + PMD_INIT_LOG(ERR, "Memory allocation failure\n"); + return -1; + } + + PMD_DRV_LOG(DEBUG, "\t Allocated DPIO Portal[%p]", dpio_dev->dpio); + dpio_dev->dpio->regs = dpio_dev->mc_portal; + if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id, + &dpio_dev->token)) { + PMD_INIT_LOG(ERR, "Failed to allocate IO space\n"); + free(dpio_dev->dpio); + return -1; + } + + if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) { + PMD_INIT_LOG(ERR, "Failed to reset dpio\n"); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + return -1; + } + + if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) { + PMD_INIT_LOG(ERR, "Failed to Enable dpio\n"); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + return -1; + } + + if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW, + dpio_dev->token, &attr)) { + PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n"); + dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + return -1; + } + + PMD_INIT_LOG(DEBUG, "Qbman Portal ID %d", attr.qbman_portal_id); + PMD_INIT_LOG(DEBUG, "Portal CE adr 0x%lX", attr.qbman_portal_ce_offset); + PMD_INIT_LOG(DEBUG, "Portal CI adr 0x%lX", attr.qbman_portal_ci_offset); + + /* Configure & setup SW portal */ + p_des.block = NULL; + p_des.idx = attr.qbman_portal_id; + p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr); + p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr); + p_des.irq = -1; + p_des.qman_version = attr.qbman_version; + + dpio_dev->sw_portal = qbman_swp_init(&p_des); + if (dpio_dev->sw_portal == NULL) { + PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n"); + dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token); + free(dpio_dev->dpio); + return -1; + } + + PMD_INIT_LOG(DEBUG, "QBMan SW Portal 0x%p\n", dpio_dev->sw_portal); + + return 0; +} + +static int +dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev) +{ + int sdest; + int cpu_id, ret; + + /* Set the Stashing Destination */ + cpu_id = rte_lcore_id(); + if (cpu_id < 0) { + cpu_id = rte_get_master_lcore(); + if (cpu_id < 0) { + RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n"); + return -1; + } + } + /* Set the STASH Destination depending on Current CPU ID. + * Valid values of SDEST are 4,5,6,7. Where, + * CPU 0-1 will have SDEST 4 + * CPU 2-3 will have SDEST 5.....and so on. + */ + + sdest = dpaa2_core_cluster_sdest(cpu_id); + PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d", + dpio_dev->index, cpu_id, sdest); + + ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW, + dpio_dev->token, sdest); + if (ret) { + PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret); + return -1; + } + + return 0; +} + +static inline struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(void) +{ + struct dpaa2_dpio_dev *dpio_dev = NULL; + int ret; + + /* Get DPIO dev handle from list using index */ + TAILQ_FOREACH(dpio_dev, dpio_dev_list, next) { + if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count)) + break; + } + if (!dpio_dev) + return NULL; + + PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu", + dpio_dev, dpio_dev->index, syscall(SYS_gettid)); + + ret = dpaa2_configure_stashing(dpio_dev); + if (ret) + PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed"); + + return dpio_dev; +} + +int +dpaa2_affine_qbman_swp(void) +{ + unsigned int lcore_id = rte_lcore_id(); + uint64_t tid = syscall(SYS_gettid); + + if (lcore_id == LCORE_ID_ANY) + lcore_id = rte_get_master_lcore(); + /* if the core id is not supported */ + else if (lcore_id >= RTE_MAX_LCORE) + return -1; + + if (dpaa2_io_portal[lcore_id].dpio_dev) { + PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared" + " between thread %lu and current %lu", + dpaa2_io_portal[lcore_id].dpio_dev, + dpaa2_io_portal[lcore_id].dpio_dev->index, + dpaa2_io_portal[lcore_id].net_tid, + tid); + RTE_PER_LCORE(_dpaa2_io).dpio_dev + = dpaa2_io_portal[lcore_id].dpio_dev; + rte_atomic16_inc(&dpaa2_io_portal + [lcore_id].dpio_dev->ref_count); + dpaa2_io_portal[lcore_id].net_tid = tid; + + PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu", + dpaa2_io_portal[lcore_id].dpio_dev, + dpaa2_io_portal[lcore_id].dpio_dev->index, + tid); + return 0; + } + + /* Populate the dpaa2_io_portal structure */ + dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(); + + if (dpaa2_io_portal[lcore_id].dpio_dev) { + RTE_PER_LCORE(_dpaa2_io).dpio_dev + = dpaa2_io_portal[lcore_id].dpio_dev; + dpaa2_io_portal[lcore_id].net_tid = tid; + + return 0; + } else { + return -1; + } +} + +int +dpaa2_create_dpio_device(struct fslmc_vfio_device *vdev, + struct vfio_device_info *obj_info, + int object_id) +{ + struct dpaa2_dpio_dev *dpio_dev; + struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)}; + + if (obj_info->num_regions < NUM_DPIO_REGIONS) { + PMD_INIT_LOG(ERR, "ERROR, Not sufficient number " + "of DPIO regions.\n"); + return -1; + } + + if (!dpio_dev_list) { + dpio_dev_list = malloc(sizeof(struct dpio_device_list)); + if (!dpio_dev_list) { + PMD_INIT_LOG(ERR, "Memory alloc failed in DPIO list\n"); + return -1; + } + + /* Initialize the DPIO List */ + TAILQ_INIT(dpio_dev_list); + } + + dpio_dev = malloc(sizeof(struct dpaa2_dpio_dev)); + if (!dpio_dev) { + PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n"); + return -1; + } + + PMD_DRV_LOG(INFO, "\t Aloocated DPIO [%p]", dpio_dev); + dpio_dev->dpio = NULL; + dpio_dev->hw_id = object_id; + dpio_dev->vfio_fd = vdev->fd; + rte_atomic16_init(&dpio_dev->ref_count); + /* Using single portal for all devices */ + dpio_dev->mc_portal = mcp_ptr_list[MC_PORTAL_INDEX]; + + reg_info.index = 0; + if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + PMD_INIT_LOG(ERR, "vfio: error getting region info\n"); + return -1; + } + + PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset); + PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size); + dpio_dev->ce_size = reg_info.size; + dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size, + PROT_WRITE | PROT_READ, MAP_SHARED, + dpio_dev->vfio_fd, reg_info.offset); + + /* Create Mapping for QBMan Cache Enabled area. This is a fix for + * SMMU fault for DQRR statshing transaction. + */ + if (vfio_dmamap_mem_region(dpio_dev->qbman_portal_ce_paddr, + reg_info.offset, reg_info.size)) { + PMD_INIT_LOG(ERR, "DMAMAP for Portal CE area failed.\n"); + return -1; + } + + reg_info.index = 1; + if (ioctl(dpio_dev->vfio_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) { + PMD_INIT_LOG(ERR, "vfio: error getting region info\n"); + return -1; + } + + PMD_DRV_LOG(DEBUG, "\t Region Offset = %llx", reg_info.offset); + PMD_DRV_LOG(DEBUG, "\t Region Size = %llx", reg_info.size); + dpio_dev->ci_size = reg_info.size; + dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size, + PROT_WRITE | PROT_READ, MAP_SHARED, + dpio_dev->vfio_fd, reg_info.offset); + + if (configure_dpio_qbman_swp(dpio_dev)) { + PMD_INIT_LOG(ERR, + "Fail to configure the dpio qbman portal for %d\n", + dpio_dev->hw_id); + return -1; + } + + io_space_count++; + dpio_dev->index = io_space_count; + TAILQ_INSERT_HEAD(dpio_dev_list, dpio_dev, next); + + return 0; +} diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h new file mode 100644 index 0000000..682f3fa --- /dev/null +++ b/drivers/bus/fslmc/portal/dpaa2_hw_dpio.h @@ -0,0 +1,60 @@ +/*- + * BSD LICENSE + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (c) 2016 NXP. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Freescale Semiconductor, Inc nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DPAA2_HW_DPIO_H_ +#define _DPAA2_HW_DPIO_H_ + +#include +#include + +struct dpaa2_io_portal_t { + struct dpaa2_dpio_dev *dpio_dev; + struct dpaa2_dpio_dev *sec_dpio_dev; + uint64_t net_tid; + uint64_t sec_tid; +}; + +/*! Global per thread DPIO portal */ +RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io); + +#define DPAA2_PER_LCORE_DPIO RTE_PER_LCORE(_dpaa2_io).dpio_dev +#define DPAA2_PER_LCORE_PORTAL DPAA2_PER_LCORE_DPIO->sw_portal + +#define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev +#define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal + +/* Affine a DPIO portal to current processing thread */ +int dpaa2_affine_qbman_swp(void); + + +#endif /* _DPAA2_HW_DPIO_H_ */ diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h new file mode 100644 index 0000000..ef3eb71 --- /dev/null +++ b/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h @@ -0,0 +1,68 @@ +/*- + * BSD LICENSE + * + * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. + * Copyright (c) 2016 NXP. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Freescale Semiconductor, Inc nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DPAA2_HW_PVT_H_ +#define _DPAA2_HW_PVT_H_ + +#include +#include + + +#define MC_PORTAL_INDEX 0 +#define NUM_DPIO_REGIONS 2 + +struct dpaa2_dpio_dev { + TAILQ_ENTRY(dpaa2_dpio_dev) next; + /**< Pointer to Next device instance */ + uint16_t index; /**< Index of a instance in the list */ + rte_atomic16_t ref_count; + /**< How many thread contexts are sharing this.*/ + struct fsl_mc_io *dpio; /** handle to DPIO portal object */ + uint16_t token; + struct qbman_swp *sw_portal; /** SW portal object */ + const struct qbman_result *dqrr[4]; + /**< DQRR Entry for this SW portal */ + void *mc_portal; /**< MC Portal for configuring this device */ + uintptr_t qbman_portal_ce_paddr; + /**< Physical address of Cache Enabled Area */ + uintptr_t ce_size; /**< Size of the CE region */ + uintptr_t qbman_portal_ci_paddr; + /**< Physical address of Cache Inhibit Area */ + uintptr_t ci_size; /**< Size of the CI region */ + int32_t vfio_fd; /**< File descriptor received via VFIO */ + int32_t hw_id; /**< An unique ID of this DPIO device instance */ +}; + +/*! Global MCP list */ +extern void *(*mcp_ptr_list); +#endif diff --git a/drivers/bus/fslmc/rte_pmd_fslmcbus_version.map b/drivers/bus/fslmc/rte_pmd_fslmcbus_version.map index 411200c..4236377 100644 --- a/drivers/bus/fslmc/rte_pmd_fslmcbus_version.map +++ b/drivers/bus/fslmc/rte_pmd_fslmcbus_version.map @@ -1,6 +1,7 @@ DPDK_17.02 { global: + dpaa2_affine_qbman_swp; dpbp_disable; dpbp_enable; dpbp_get_attributes; @@ -46,6 +47,7 @@ DPDK_17.02 { dpseci_reset; dpseci_set_rx_queue; mcp_ptr_list; + per_lcore__dpaa2_io; rte_fslmc_driver_register; rte_fslmc_driver_unregister; vfio_dmamap_mem_region; diff --git a/drivers/common/Makefile b/drivers/common/Makefile index 76ec2d1..434280f 100644 --- a/drivers/common/Makefile +++ b/drivers/common/Makefile @@ -33,6 +33,10 @@ include $(RTE_SDK)/mk/rte.vars.mk CONFIG_RTE_LIBRTE_DPAA2_COMMON = $(CONFIG_RTE_LIBRTE_DPAA2_PMD) +ifneq ($(CONFIG_RTE_LIBRTE_DPAA2_COMMON),y) +CONFIG_RTE_LIBRTE_DPAA2_COMMON = $(CONFIG_RTE_LIBRTE_FSLMC_BUS) +endif + DIRS-$(CONFIG_RTE_LIBRTE_DPAA2_COMMON) += dpaa2 include $(RTE_SDK)/mk/rte.subdir.mk