From patchwork Tue Sep 19 01:29:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mody, Rasesh" X-Patchwork-Id: 28876 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E2812199A9; Tue, 19 Sep 2017 03:31:12 +0200 (CEST) Received: from NAM02-CY1-obe.outbound.protection.outlook.com (mail-cys01nam02on0061.outbound.protection.outlook.com [104.47.37.61]) by dpdk.org (Postfix) with ESMTP id F3C0A25A1 for ; Tue, 19 Sep 2017 03:31:10 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=LG6vxq0AEYocUtvymvrhmRgDLPICwfgfIJOsJ6wLMi0=; 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X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2017 01:31:08.8085 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR0701MB3838 Subject: [dpdk-dev] [PATCH 01/53] net/qede/base: add NVM config options X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add new NVM configuration options like - enabling Preboot Debug Mode, - 20G ethernet backplane support, - add RDMA to NPAR protocol list, - PHY module temperature thresholds, etc. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/nvm_cfg.h | 63 ++++++++++++++++++++++++++++++++------- 1 file changed, 53 insertions(+), 10 deletions(-) diff --git a/drivers/net/qede/base/nvm_cfg.h b/drivers/net/qede/base/nvm_cfg.h index 4e58835..ccd9286 100644 --- a/drivers/net/qede/base/nvm_cfg.h +++ b/drivers/net/qede/base/nvm_cfg.h @@ -13,20 +13,20 @@ * Description: NVM config file - Generated file from nvm cfg excel. * DO NOT MODIFY !!! * - * Created: 12/15/2016 + * Created: 4/10/2017 * ****************************************************************************/ #ifndef NVM_CFG_H #define NVM_CFG_H -#define NVM_CFG_version 0x81805 +#define NVM_CFG_version 0x83000 -#define NVM_CFG_new_option_seq 15 +#define NVM_CFG_new_option_seq 22 -#define NVM_CFG_removed_option_seq 0 +#define NVM_CFG_removed_option_seq 1 -#define NVM_CFG_updated_value_seq 1 +#define NVM_CFG_updated_value_seq 4 struct nvm_cfg_mac_address { u32 mac_addr_hi; @@ -509,6 +509,10 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_PF_MAPPING_OFFSET 26 #define NVM_CFG1_GLOB_PF_MAPPING_CONTINUOUS 0x0 #define NVM_CFG1_GLOB_PF_MAPPING_FIXED 0x1 + #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_MASK 0x30000000 + #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28 + #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0 + #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1 u32 led_global_settings; /* 0x74 */ #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 @@ -1036,7 +1040,9 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 - u32 reserved[58]; /* 0x140 */ + u32 preboot_debug_mode_std; /* 0x140 */ + u32 preboot_debug_mode_ext; /* 0x144 */ + u32 reserved[56]; /* 0x148 */ }; struct nvm_cfg1_path { @@ -1134,6 +1140,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1142,6 +1149,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1152,6 +1160,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 @@ -1167,6 +1176,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MFW_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6 @@ -1276,6 +1286,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6 @@ -1289,6 +1300,8 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_RESERVED65_OFFSET 0 #define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000 #define NVM_CFG1_PORT_RESERVED66_OFFSET 16 + #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_MASK 0x01FE0000 + #define NVM_CFG1_PORT_PREBOOT_LINK_UP_DELAY_OFFSET 17 u32 vf_cfg; /* 0x30 */ #define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF #define NVM_CFG1_PORT_RESERVED8_OFFSET 0 @@ -1304,9 +1317,12 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2 - #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8 - #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10 - #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_25G 0x4 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_25G 0x8 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_40G 0x8 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_40G 0x10 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 + #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 u32 transceiver_00; /* 0x40 */ /* Define for mapping of transceiver signal module absent */ @@ -1412,6 +1428,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1423,6 +1440,7 @@ struct nvm_cfg1_port { 16 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1434,6 +1452,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6 @@ -1444,6 +1463,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6 @@ -1490,6 +1510,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1501,6 +1522,7 @@ struct nvm_cfg1_port { 16 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1512,6 +1534,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6 @@ -1522,6 +1545,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6 @@ -1568,6 +1592,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1579,6 +1604,7 @@ struct nvm_cfg1_port { 16 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1590,6 +1616,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6 @@ -1600,6 +1627,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6 @@ -1646,6 +1674,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1658,6 +1687,7 @@ struct nvm_cfg1_port { 16 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20 @@ -1670,6 +1700,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6 @@ -1680,6 +1711,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6 @@ -1726,6 +1758,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20 @@ -1735,6 +1768,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2 + #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_20G 0x4 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10 #define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20 @@ -1745,6 +1779,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6 @@ -1755,6 +1790,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2 + #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_20G 0x3 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5 #define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6 @@ -1795,7 +1831,13 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2 #define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_AUTO 0x7 - u32 reserved[116]; /* 0x88 */ + u32 temperature; /* 0x88 */ + #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_MASK 0x000000FF + #define NVM_CFG1_PORT_PHY_MODULE_DEAD_TEMP_TH_OFFSET 0 + #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK \ + 0x0000FF00 + #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 + u32 reserved[115]; /* 0x8C */ }; struct nvm_cfg1_func { @@ -1910,6 +1952,7 @@ struct nvm_cfg1_func { #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ETHERNET 0x1 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_FCOE 0x2 #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_ISCSI 0x4 + #define NVM_CFG1_FUNC_NPAR_ENABLED_PROTOCOL_RDMA 0x8 u32 reserved[8]; /* 0x30 */ };