From patchwork Tue May 29 11:53:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Wang, Haiyue" X-Patchwork-Id: 40504 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 16F832F7D; Tue, 29 May 2018 13:53:09 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by dpdk.org (Postfix) with ESMTP id 71F09F72; Tue, 29 May 2018 13:53:06 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 May 2018 04:53:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,456,1520924400"; d="scan'208";a="203533553" Received: from build-dpdk-2600wfp.sh.intel.com ([10.67.111.114]) by orsmga004.jf.intel.com with ESMTP; 29 May 2018 04:53:03 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: Haiyue Wang , stable@dpdk.org Date: Tue, 29 May 2018 19:53:06 +0800 Message-Id: <1527594786-83831-1-git-send-email-haiyue.wang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1527583036-6062-1-git-send-email-haiyue.wang@intel.com> References: <1527583036-6062-1-git-send-email-haiyue.wang@intel.com> Subject: [dpdk-dev] [PATCH v2] net/i40e: workaround for Fortville performance X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The GL_SWR_PM_UP_THR value is not impacted from the link speed, its value is set according to the total number of ports for a better pipe-monitor configuration. All bellowing relevant device IDs are considered (NICs, LOMs, Mezz and Backplane): Device-ID Value Comments 0x1572 0x03030303 10G SFI 0x1581 0x03030303 10G Backplane 0x1586 0x03030303 10G BaseT 0x1589 0x03030303 10G BaseT (FortPond) 0x1580 0x06060606 40G Backplane 0x1583 0x06060606 2x40G QSFP 0x1584 0x06060606 1x40G QSFP 0x1587 0x06060606 20G Backplane (HP) 0x1588 0x06060606 20G KR2 (HP) 0x158A 0x06060606 25G Backplane 0x158B 0x06060606 25G SFP28 Fixes: c9223a2bf53c ("i40e: workaround for XL710 performance") Fixes: 75d133dd3296 ("net/i40e: enable 25G device") Cc: stable@dpdk.org Signed-off-by: Haiyue Wang --- drivers/net/i40e/i40e_ethdev.c | 71 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 64 insertions(+), 7 deletions(-) --- v1 -> v2: - The GL_SWR_PM_UP_THR register size is 4B, so change the table value type from uint64_t to uint32_t to reduce the table size. - Fix two CAMELCASE coding style errors. diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 7d4f1c9..95274f3 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -10003,6 +10003,60 @@ enum i40e_filter_pctype #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606 #define I40E_GL_SWR_PM_UP_THR 0x269FBC +/* + * GL_SWR_PM_UP_THR: + * The value is not impacted from the link speed, its value is set according + * to the total number of ports for a better pipe-monitor configuration. + */ +static int +i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value) +{ +#define I40E_GL_SWR_PM_EF_DEVICE(dev) \ + .device_id = (dev), \ + .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE + +#define I40E_GL_SWR_PM_SF_DEVICE(dev) \ + .device_id = (dev), \ + .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE + + static const struct { + uint16_t device_id; + uint32_t val; + } swr_pm_table[] = { + { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) }, + { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) }, + { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) }, + { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) }, + + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) }, + { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) }, + }; + uint32_t i; + + if (value == NULL) { + PMD_DRV_LOG(ERR, "value is NULL"); + return 0; + } + + for (i = 0; i < RTE_DIM(swr_pm_table); i++) { + if (hw->device_id == swr_pm_table[i].device_id) { + *value = swr_pm_table[i].val; + + PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR " + "value - 0x%08x", + hw->device_id, *value); + return 1; + } + } + + return 0; +} + static int i40e_dev_sync_phy_type(struct i40e_hw *hw) { @@ -10067,13 +10121,16 @@ enum i40e_filter_pctype } if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) { - if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */ - I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */ - reg_table[i].val = - I40E_GL_SWR_PM_UP_THR_SF_VALUE; - else /* For X710 */ - reg_table[i].val = - I40E_GL_SWR_PM_UP_THR_EF_VALUE; + uint32_t cfg_val; + + if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) { + PMD_DRV_LOG(DEBUG, "Device 0x%x skips " + "GL_SWR_PM_UP_THR value fixup", + hw->device_id); + continue; + } + + reg_table[i].val = cfg_val; } ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,