From patchwork Thu Feb 7 16:29:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 50208 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CCC9E1B5CC; Thu, 7 Feb 2019 17:30:52 +0100 (CET) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id 96B321B579 for ; Thu, 7 Feb 2019 17:30:36 +0100 (CET) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us3.ppe-hosted.com (Proofpoint Essentials ESMTP Server) with ESMTPS id D941AB80105; Thu, 7 Feb 2019 16:30:34 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 7 Feb 2019 08:30:30 -0800 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 7 Feb 2019 08:30:30 -0800 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id x17GUT2T015272; Thu, 7 Feb 2019 16:30:29 GMT Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id 561C31613ED; Thu, 7 Feb 2019 16:30:29 +0000 (GMT) From: Andrew Rybchenko To: CC: Igor Romanov Date: Thu, 7 Feb 2019 16:29:11 +0000 Message-ID: <1549556983-10896-7-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1549556983-10896-1-git-send-email-arybchenko@solarflare.com> References: <1549556983-10896-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24412.006 X-TM-AS-Result: No-9.543800-4.000000-10 X-TMASE-MatchedRID: sz2FKyi+8PAnKzXFbJ7zRR+WEMjoO9WWTJDl9FKHbrl+CPuoK+vfzQZv 5imTddffiDmMb1VWfPfUQFfJkJ1IVC0kxsNYPyne4pdq9sdj8LWH7D1bP/FcOiAdcfr1cZRDo8W MkQWv6iXBcIE78YqRWo6HM5rqDwqtHG2Zcn0VIa+QFVnn8brCqv/lbW+OxF+4pryDPkPW8UpBJv RUZ4vP1UMMprcbiest X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--9.543800-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24412.006 X-MDID: 1549557035-YAZAmG-a_jkm Subject: [dpdk-dev] [PATCH 06/38] net/sfc/base: define max desc number for every EF10 NIC X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Igor Romanov For consistency with defines of min descriptor number, define max descriptor number for Huntington, Medford and Medford2. Signed-off-by: Igor Romanov Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/base/hunt_impl.h | 3 +++ drivers/net/sfc/base/hunt_nic.c | 4 +++- drivers/net/sfc/base/medford2_impl.h | 2 ++ drivers/net/sfc/base/medford2_nic.c | 2 +- drivers/net/sfc/base/medford_impl.h | 2 ++ drivers/net/sfc/base/medford_nic.c | 2 +- 6 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/net/sfc/base/hunt_impl.h b/drivers/net/sfc/base/hunt_impl.h index d8dddce8d..0e9a1e280 100644 --- a/drivers/net/sfc/base/hunt_impl.h +++ b/drivers/net/sfc/base/hunt_impl.h @@ -16,6 +16,9 @@ extern "C" { #endif +#define HUNT_TXQ_MAXNDESCS 4096 +#define HUNT_TXQ_MAXNDESCS_BUG35388_WORKAROUND 2048 + /* Missing register definitions */ #ifndef ER_DZ_TX_PIOBUF_OFST #define ER_DZ_TX_PIOBUF_OFST 0x00001000 diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c index adb2b17eb..6605cfce4 100644 --- a/drivers/net/sfc/base/hunt_nic.c +++ b/drivers/net/sfc/base/hunt_nic.c @@ -194,7 +194,9 @@ hunt_board_cfg( * The workaround for bug35388 uses the top bit of transmit queue * descriptor writes, preventing the use of 4096 descriptor TXQs. */ - encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096; + encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? + HUNT_TXQ_MAXNDESCS_BUG35388_WORKAROUND : + HUNT_TXQ_MAXNDESCS; encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); diff --git a/drivers/net/sfc/base/medford2_impl.h b/drivers/net/sfc/base/medford2_impl.h index 6259a700b..87af5f686 100644 --- a/drivers/net/sfc/base/medford2_impl.h +++ b/drivers/net/sfc/base/medford2_impl.h @@ -12,6 +12,8 @@ extern "C" { #endif +#define MEDFORD2_TXQ_MAXNDESCS 2048 + #ifndef ER_EZ_TX_PIOBUF_SIZE #define ER_EZ_TX_PIOBUF_SIZE 4096 #endif diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c index 2cc87e3a9..020c37fd9 100644 --- a/drivers/net/sfc/base/medford2_nic.c +++ b/drivers/net/sfc/base/medford2_nic.c @@ -119,7 +119,7 @@ medford2_board_cfg( * descriptors are not supported as the top bit is used for vfifo * stuffing. */ - encp->enc_txq_max_ndescs = 2048; + encp->enc_txq_max_ndescs = MEDFORD2_TXQ_MAXNDESCS; encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS); diff --git a/drivers/net/sfc/base/medford_impl.h b/drivers/net/sfc/base/medford_impl.h index d076afa2d..1afedc7f3 100644 --- a/drivers/net/sfc/base/medford_impl.h +++ b/drivers/net/sfc/base/medford_impl.h @@ -12,6 +12,8 @@ extern "C" { #endif +#define MEDFORD_TXQ_MAXNDESCS 2048 + #ifndef ER_EZ_TX_PIOBUF_SIZE #define ER_EZ_TX_PIOBUF_SIZE 4096 #endif diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c index b72881179..171e39b03 100644 --- a/drivers/net/sfc/base/medford_nic.c +++ b/drivers/net/sfc/base/medford_nic.c @@ -117,7 +117,7 @@ medford_board_cfg( * descriptors are not supported as the top bit is used for vfifo * stuffing. */ - encp->enc_txq_max_ndescs = 2048; + encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS; encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS; EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);