diff --git a/drivers/raw/ifpga_rawdev/base/Makefile b/drivers/raw/ifpga_rawdev/base/Makefile
index c6f51a8..edb538f 100644
--- a/drivers/raw/ifpga_rawdev/base/Makefile
+++ b/drivers/raw/ifpga_rawdev/base/Makefile
@@ -25,5 +25,7 @@ SRCS-y += ifpga_fme_pr.c
 SRCS-y += opae_spi.c
 SRCS-y += opae_spi_transaction.c
 SRCS-y += opae_intel_max10.c
+SRCS-y += opae_i2c.c
+SRCS-y += opae_at24_eeprom.c
 
 SRCS-y += $(wildcard $(SRCDIR)/base/$(OSDEP)/*.c)
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_api.c b/drivers/raw/ifpga_rawdev/base/ifpga_api.c
index 77d9471..c447b3c 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_api.c
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_api.c
@@ -196,6 +196,28 @@ struct opae_manager_ops ifpga_mgr_ops = {
 	.flash = ifpga_mgr_flash,
 };
 
+static int ifpga_mgr_read_mac_rom(struct opae_manager *mgr, int offset,
+		void *buf, int size)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	return fme_mgr_read_mac_rom(fme, offset, buf, size);
+}
+
+static int ifpga_mgr_write_mac_rom(struct opae_manager *mgr, int offset,
+		void *buf, int size)
+{
+	struct ifpga_fme_hw *fme = mgr->data;
+
+	return fme_mgr_write_mac_rom(fme, offset, buf, size);
+}
+
+/* Network APIs in FME */
+struct opae_manager_networking_ops ifpga_mgr_network_ops = {
+	.read_mac_rom = ifpga_mgr_read_mac_rom,
+	.write_mac_rom = ifpga_mgr_write_mac_rom,
+};
+
 /* Adapter APIs */
 static int ifpga_adapter_enumerate(struct opae_adapter *adapter)
 {
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_api.h b/drivers/raw/ifpga_rawdev/base/ifpga_api.h
index dae7ca1..4a24769 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_api.h
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_api.h
@@ -12,6 +12,7 @@
 extern struct opae_manager_ops ifpga_mgr_ops;
 extern struct opae_bridge_ops ifpga_br_ops;
 extern struct opae_accelerator_ops ifpga_acc_ops;
+extern struct opae_manager_networking_ops ifpga_mgr_network_ops;
 
 /* common APIs */
 int ifpga_get_prop(struct ifpga_hw *hw, u32 fiu_id, u32 port_id,
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
index f5e22ae..62f71c7 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_defines.h
@@ -21,6 +21,7 @@
 #define FME_FEATURE_QSPI_FLASH	    "fme_qspi_flash"
 #define FME_FEATURE_MAX10_SPI       "fme_max10_spi"
 #define FME_FEATURE_NIOS_SPI        "fme_nios_spi"
+#define FME_FEATURE_I2C_MASTER      "fme_i2c_master"
 
 #define PORT_FEATURE_HEADER         "port_hdr"
 #define PORT_FEATURE_UAFU           "port_uafu"
@@ -46,6 +47,7 @@
 #define FME_GLOBAL_DPERF_REVISION	0
 #define FME_QSPI_REVISION		0
 #define FME_MAX10_SPI                   0
+#define FME_I2C_MASTER                  0
 
 #define PORT_HEADER_REVISION		0
 /* UAFU's header info depends on the downloaded GBS */
@@ -85,6 +87,7 @@ enum fpga_id_type {
 #define FME_FEATURE_ID_EMIF_MGMT  0x9
 #define FME_FEATURE_ID_MAX10_SPI  0xe
 #define FME_FEATURE_ID_NIOS_SPI 0xd
+#define FME_FEATURE_ID_I2C_MASTER  0xf
 
 #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
 #define PORT_FEATURE_ID_ERROR 0x10
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c b/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c
index c779e0c..666dae1 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_enumerate.c
@@ -270,7 +270,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
 
 	} else if (binfo->current_type == FME_ID) {
 		mgr = opae_manager_alloc(hw->adapter->name, &ifpga_mgr_ops,
-				binfo->fiu);
+				&ifpga_mgr_network_ops, binfo->fiu);
 		if (!mgr)
 			return -ENOMEM;
 
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c
index 2a35c06..0454f80 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.c
@@ -201,6 +201,8 @@ int port_clear_error(struct ifpga_port_hw *port)
 	&fme_spi_master_ops),},
 	{FEATURE_DRV(FME_FEATURE_ID_NIOS_SPI, FME_FEATURE_NIOS_SPI,
 	&fme_nios_spi_master_ops),},
+	{FEATURE_DRV(FME_FEATURE_ID_I2C_MASTER, FME_FEATURE_I2C_MASTER,
+	&fme_i2c_master_ops),},
 	{0, NULL, NULL}, /* end of arrary */
 };
 
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h
index 72352ee..a398a98 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_feature_dev.h
@@ -172,6 +172,7 @@ int do_pr(struct ifpga_hw *hw, u32 port_id, void *buffer, u32 size,
 extern struct feature_ops fme_hssi_eth_ops;
 extern struct feature_ops fme_emif_ops;
 extern struct feature_ops fme_spi_master_ops;
+extern struct feature_ops fme_i2c_master_ops;
 extern struct feature_ops fme_nios_spi_master_ops;
 
 int port_get_prop(struct ifpga_port_hw *port, struct feature_prop *prop);
@@ -197,4 +198,10 @@ struct fpga_uafu_irq_set {
 /* help functions for feature ops */
 int fpga_msix_set_block(struct feature *feature, unsigned int start,
 			unsigned int count, s32 *fds);
+
+/* FME network function ops*/
+int fme_mgr_read_mac_rom(struct ifpga_fme_hw *fme, int offset,
+		void *buf, int size);
+int fme_mgr_write_mac_rom(struct ifpga_fme_hw *fme, int offset,
+		void *buf, int size);
 #endif /* _IFPGA_FEATURE_DEV_H_ */
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_fme.c b/drivers/raw/ifpga_rawdev/base/ifpga_fme.c
index 28226f0..95e022e 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_fme.c
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_fme.c
@@ -5,6 +5,8 @@
 #include "ifpga_feature_dev.h"
 #include "opae_spi.h"
 #include "opae_intel_max10.h"
+#include "opae_i2c.h"
+#include "opae_at24_eeprom.h"
 
 #define PWR_THRESHOLD_MAX       0x7F
 
@@ -960,3 +962,91 @@ struct feature_ops fme_nios_spi_master_ops = {
 	.init = fme_nios_spi_init,
 	.uinit = fme_nios_spi_uinit,
 };
+
+static int i2c_mac_rom_test(struct altera_i2c_dev *dev)
+{
+	char buf[20];
+	int ret;
+	char read_buf[20] = {0,};
+	const char *string = "1a2b3c4d5e";
+
+	opae_memcpy(buf, string, strlen(string));
+
+	ret = at24_eeprom_write(dev, AT24512_SLAVE_ADDR, 0,
+			(u8 *)buf, strlen(string));
+	if (ret < 0) {
+		dev_err(NULL, "write i2c error:%d\n", ret);
+		return ret;
+	}
+
+	ret = at24_eeprom_read(dev, AT24512_SLAVE_ADDR, 0,
+			(u8 *)read_buf, strlen(string));
+	if (ret < 0) {
+		dev_err(NULL, "read i2c error:%d\n", ret);
+		return ret;
+	}
+
+	if (memcmp(buf, read_buf, strlen(string))) {
+		dev_err(NULL, "%s test fail!\n", __func__);
+		return -EFAULT;
+	}
+
+	dev_info(NULL, "%s test successful\n", __func__);
+
+	return 0;
+}
+
+static int fme_i2c_init(struct feature *feature)
+{
+	struct feature_fme_i2c *i2c;
+	struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
+
+	i2c = (struct feature_fme_i2c *)feature->addr;
+
+	dev_info(NULL, "FME I2C Master Init.\n");
+
+	fme->i2c_master = altera_i2c_probe(i2c);
+	if (!fme->i2c_master)
+		return -ENODEV;
+
+	/* MAC ROM self test */
+	i2c_mac_rom_test(fme->i2c_master);
+
+	return 0;
+}
+
+static void fme_i2c_uninit(struct feature *feature)
+{
+	struct ifpga_fme_hw *fme = (struct ifpga_fme_hw *)feature->parent;
+
+	altera_i2c_remove(fme->i2c_master);
+}
+
+struct feature_ops fme_i2c_master_ops = {
+	.init = fme_i2c_init,
+	.uinit = fme_i2c_uninit,
+};
+
+int fme_mgr_read_mac_rom(struct ifpga_fme_hw *fme, int offset,
+		void *buf, int size)
+{
+	struct altera_i2c_dev *dev;
+
+	dev = fme->i2c_master;
+	if (!dev)
+		return -ENODEV;
+
+	return at24_eeprom_read(dev, AT24512_SLAVE_ADDR, offset, buf, size);
+}
+
+int fme_mgr_write_mac_rom(struct ifpga_fme_hw *fme, int offset,
+		void *buf, int size)
+{
+	struct altera_i2c_dev *dev;
+
+	dev = fme->i2c_master;
+	if (!dev)
+		return -ENODEV;
+
+	return at24_eeprom_write(dev, AT24512_SLAVE_ADDR, offset, buf, size);
+}
diff --git a/drivers/raw/ifpga_rawdev/base/ifpga_hw.h b/drivers/raw/ifpga_rawdev/base/ifpga_hw.h
index a2f4776..e296dd2 100644
--- a/drivers/raw/ifpga_rawdev/base/ifpga_hw.h
+++ b/drivers/raw/ifpga_rawdev/base/ifpga_hw.h
@@ -81,6 +81,7 @@ struct ifpga_fme_hw {
 	u32 capability;
 
 	void *max10_dev; /* MAX10 device */
+	void *i2c_master; /* I2C Master device */
 };
 
 enum ifpga_port_state {
diff --git a/drivers/raw/ifpga_rawdev/base/meson.build b/drivers/raw/ifpga_rawdev/base/meson.build
index 6bc762f..7655985 100644
--- a/drivers/raw/ifpga_rawdev/base/meson.build
+++ b/drivers/raw/ifpga_rawdev/base/meson.build
@@ -18,6 +18,8 @@ sources = [
 	'opae_spi.c',
 	'opae_spi_transaction.c',
 	'opae_intel_max10.c',
+	'opae_i2c.c',
+	'opae_at24_eeprom.c',
 ]
 
 error_cflags = ['-Wno-sign-compare', '-Wno-unused-value',
diff --git a/drivers/raw/ifpga_rawdev/base/opae_at24_eeprom.c b/drivers/raw/ifpga_rawdev/base/opae_at24_eeprom.c
new file mode 100644
index 0000000..d70f7af
--- /dev/null
+++ b/drivers/raw/ifpga_rawdev/base/opae_at24_eeprom.c
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2019 Intel Corporation
+ */
+
+#include "opae_osdep.h"
+#include "opae_i2c.h"
+#include "opae_at24_eeprom.h"
+
+#define AT24_READ_RETRY 10
+
+static int at24_eeprom_read_and_try(struct altera_i2c_dev *dev,
+		unsigned int slave_addr,
+		u32 offset, u8 *buf, u32 len)
+{
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < AT24_READ_RETRY; i++) {
+		ret = i2c_read16(dev, slave_addr, offset,
+				buf, len);
+		if (ret == 0)
+			break;
+
+		opae_udelay(100);
+	}
+
+	return ret;
+}
+
+int at24_eeprom_read(struct altera_i2c_dev *dev, unsigned int slave_addr,
+		u32 offset, u8 *buf, int count)
+{
+	int len;
+	int status;
+	int read_count = 0;
+
+	if (!count)
+		return count;
+
+	if (count > AT24C512_IO_LIMIT)
+		len = AT24C512_IO_LIMIT;
+	else
+		len = count;
+
+	while (count) {
+		status = at24_eeprom_read_and_try(dev, slave_addr, offset,
+				buf, len);
+		if (status)
+			break;
+
+		buf += len;
+		offset += len;
+		count -= len;
+		read_count += len;
+	}
+
+	return read_count;
+}
+
+int at24_eeprom_write(struct altera_i2c_dev *dev, unsigned int slave_addr,
+		u32 offset, u8 *buf, int count)
+{
+	int len;
+	int status;
+	int write_count = 0;
+
+	if (!count)
+		return count;
+
+	if (count > AT24C512_PAGE_SIZE)
+		len = AT24C512_PAGE_SIZE;
+	else
+		len = count;
+
+	while (count) {
+		status = i2c_write16(dev, slave_addr, offset, buf, len);
+		if (status)
+			break;
+
+		buf += len;
+		offset += len;
+		count -= len;
+		write_count += len;
+	}
+
+	return write_count;
+}
+
diff --git a/drivers/raw/ifpga_rawdev/base/opae_at24_eeprom.h b/drivers/raw/ifpga_rawdev/base/opae_at24_eeprom.h
new file mode 100644
index 0000000..caae9a3
--- /dev/null
+++ b/drivers/raw/ifpga_rawdev/base/opae_at24_eeprom.h
@@ -0,0 +1,14 @@
+
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2019 Intel Corporation
+ */
+
+#define AT24C512_PAGE_SIZE 128
+#define AT24C512_IO_LIMIT  128
+
+#define AT24512_SLAVE_ADDR 0x51
+
+int at24_eeprom_read(struct altera_i2c_dev *dev, unsigned int slave_addr,
+		u32 offset, u8 *buf, int count);
+int at24_eeprom_write(struct altera_i2c_dev *dev, unsigned int slave_addr,
+		u32 offset, u8 *buf, int count);
diff --git a/drivers/raw/ifpga_rawdev/base/opae_hw_api.c b/drivers/raw/ifpga_rawdev/base/opae_hw_api.c
index 41c5903..ec2b4c7 100644
--- a/drivers/raw/ifpga_rawdev/base/opae_hw_api.c
+++ b/drivers/raw/ifpga_rawdev/base/opae_hw_api.c
@@ -210,12 +210,14 @@ int opae_acc_get_uuid(struct opae_accelerator *acc,
  * opae_manager_alloc - alloc opae_manager data structure
  * @name: manager name.
  * @ops: ops of this manager.
+ * @network_ops: ops of network management.
  * @data: private data of this manager.
  *
  * Return: opae_manager on success, otherwise NULL.
  */
 struct opae_manager *
-opae_manager_alloc(const char *name, struct opae_manager_ops *ops, void *data)
+opae_manager_alloc(const char *name, struct opae_manager_ops *ops,
+		struct opae_manager_networking_ops *network_ops, void *data)
 {
 	struct opae_manager *mgr = opae_zmalloc(sizeof(*mgr));
 
@@ -224,6 +226,7 @@ struct opae_manager *
 
 	mgr->name = name;
 	mgr->ops = ops;
+	mgr->network_ops = network_ops;
 	mgr->data = data;
 
 	opae_log("%s %p\n", __func__, mgr);
@@ -379,3 +382,47 @@ struct opae_accelerator *
 
 	return NULL;
 }
+
+/**
+ * opae_manager_read_mac_rom - read the content of the MAC ROM
+ * @mgr: opae_manager for MAC ROM
+ * @port: the port number of retimer
+ * @addr: buffer of the MAC address
+ *
+ * Return: return the bytes of read successfully
+ */
+int opae_manager_read_mac_rom(struct opae_manager *mgr, int port,
+		struct opae_ether_addr *addr)
+{
+	if (!mgr || !mgr->network_ops)
+		return -EINVAL;
+
+	if (mgr->network_ops->read_mac_rom)
+		return mgr->network_ops->read_mac_rom(mgr,
+				port * sizeof(struct opae_ether_addr),
+				addr, sizeof(struct opae_ether_addr));
+
+	return -ENOENT;
+}
+
+/**
+ * opae_manager_write_mac_rom - write data into MAC ROM
+ * @mgr: opae_manager for MAC ROM
+ * @port: the port number of the retimer
+ * @addr: data of the MAC address
+ *
+ * Return: return written bytes
+ */
+int opae_manager_write_mac_rom(struct opae_manager *mgr, int port,
+		struct opae_ether_addr *addr)
+{
+	if (!mgr || !mgr->network_ops)
+		return -EINVAL;
+
+	if (mgr->network_ops && mgr->network_ops->write_mac_rom)
+		return mgr->network_ops->write_mac_rom(mgr,
+				port * sizeof(struct opae_ether_addr),
+				addr, sizeof(struct opae_ether_addr));
+
+	return -ENOENT;
+}
diff --git a/drivers/raw/ifpga_rawdev/base/opae_hw_api.h b/drivers/raw/ifpga_rawdev/base/opae_hw_api.h
index 76224b4..826da37 100644
--- a/drivers/raw/ifpga_rawdev/base/opae_hw_api.h
+++ b/drivers/raw/ifpga_rawdev/base/opae_hw_api.h
@@ -26,6 +26,7 @@ enum opae_adapter_type {
 
 /* OPAE Manager Data Structure */
 struct opae_manager_ops;
+struct opae_manager_networking_ops;
 
 /*
  * opae_manager has pointer to its parent adapter, as it could be able to manage
@@ -36,6 +37,7 @@ struct opae_manager {
 	const char *name;
 	struct opae_adapter *adapter;
 	struct opae_manager_ops *ops;
+	struct opae_manager_networking_ops *network_ops;
 	void *data;
 };
 
@@ -45,9 +47,18 @@ struct opae_manager_ops {
 		     u32 size, u64 *status);
 };
 
+/* networking management ops in FME */
+struct opae_manager_networking_ops {
+	int (*read_mac_rom)(struct opae_manager *mgr, int offset, void *buf,
+			int size);
+	int (*write_mac_rom)(struct opae_manager *mgr, int offset, void *buf,
+			int size);
+};
+
 /* OPAE Manager APIs */
 struct opae_manager *
-opae_manager_alloc(const char *name, struct opae_manager_ops *ops, void *data);
+opae_manager_alloc(const char *name, struct opae_manager_ops *ops,
+		struct opae_manager_networking_ops *network_ops, void *data);
 #define opae_manager_free(mgr) opae_free(mgr)
 int opae_manager_flash(struct opae_manager *mgr, int acc_id, void *buf,
 		       u32 size, u64 *status);
@@ -252,4 +263,17 @@ static inline void opae_adapter_remove_acc(struct opae_adapter *adapter,
 {
 	TAILQ_REMOVE(&adapter->acc_list, acc, node);
 }
+
+/* OPAE vBNG network datastruct */
+#define OPAE_ETHER_ADDR_LEN 6
+
+struct opae_ether_addr {
+	unsigned char addr_bytes[OPAE_ETHER_ADDR_LEN];
+} __attribute__((__packed__));
+
+/* OPAE vBNG network API*/
+int opae_manager_read_mac_rom(struct opae_manager *mgr, int port,
+		struct opae_ether_addr *addr);
+int opae_manager_write_mac_rom(struct opae_manager *mgr, int port,
+		struct opae_ether_addr *addr);
 #endif /* _OPAE_HW_API_H_*/
diff --git a/drivers/raw/ifpga_rawdev/base/opae_i2c.c b/drivers/raw/ifpga_rawdev/base/opae_i2c.c
new file mode 100644
index 0000000..f8bc247
--- /dev/null
+++ b/drivers/raw/ifpga_rawdev/base/opae_i2c.c
@@ -0,0 +1,490 @@
+
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2019 Intel Corporation
+ */
+
+#include "opae_osdep.h"
+#include "opae_i2c.h"
+
+static int i2c_transfer(struct altera_i2c_dev *dev,
+		struct i2c_msg *msg, int num)
+{
+	int ret, try;
+
+	for (ret = 0, try = 0; try < I2C_XFER_RETRY; try++) {
+		ret = dev->xfer(dev, msg, num);
+		if (ret != -EAGAIN)
+			break;
+	}
+
+	return ret;
+}
+
+/**
+ * i2c read function
+ */
+int i2c_read(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
+		u32 offset, u8 *buf, u32 count)
+{
+	u8 msgbuf[2];
+	int i = 0;
+
+	if (flags & I2C_FLAG_ADDR16)
+		msgbuf[i++] = offset >> 8;
+
+	msgbuf[i++] = offset;
+
+	struct i2c_msg msg[2] = {
+		{
+			.addr = slave_addr,
+			.flags = 0,
+			.len = i,
+			.buf = msgbuf,
+		},
+		{
+			.addr = slave_addr,
+			.flags = I2C_M_RD,
+			.len = count,
+			.buf = buf,
+		},
+	};
+
+	if (!dev->xfer)
+		return -ENODEV;
+
+	return i2c_transfer(dev, msg, 2);
+}
+
+int i2c_write(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
+		u32 offset, u8 *buffer, int len)
+{
+	struct i2c_msg msg;
+	u8 *buf;
+	int ret;
+	int i = 0;
+
+	if (!dev->xfer)
+		return -ENODEV;
+
+	buf = opae_malloc(I2C_MAX_OFFSET_LEN + len);
+	if (!buf)
+		return -ENOMEM;
+
+	msg.addr = slave_addr;
+	msg.flags = 0;
+	msg.buf = buf;
+
+	if (flags & I2C_FLAG_ADDR16)
+		msg.buf[i++] = offset >> 8;
+
+	msg.buf[i++] = offset;
+	opae_memcpy(&msg.buf[i], buffer, len);
+	msg.len = i + len;
+
+	ret = i2c_transfer(dev, &msg, 1);
+
+	opae_free(buf);
+	return ret;
+}
+
+int i2c_read8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
+		u8 *buf, u32 count)
+{
+	return i2c_read(dev, 0, slave_addr, offset, buf, count);
+}
+
+int i2c_read16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
+		u8 *buf, u32 count)
+{
+	return i2c_read(dev, I2C_FLAG_ADDR16, slave_addr, offset,
+			buf, count);
+}
+
+int i2c_write8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
+		u8 *buf, u32 count)
+{
+	return i2c_write(dev, 0, slave_addr, offset, buf, count);
+}
+
+int i2c_write16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
+		u8 *buf, u32 count)
+{
+	return i2c_write(dev, I2C_FLAG_ADDR16, slave_addr, offset,
+			buf, count);
+}
+
+static void i2c_indirect_write(struct altera_i2c_dev *dev, u32 reg,
+		u32 value)
+{
+	u64 ctrl;
+
+	ctrl = I2C_CTRL_W | (reg >> 2);
+
+	opae_writeq(value & I2C_WRITE_DATA_MASK, dev->base + I2C_WRITE);
+	opae_writeq(ctrl, dev->base + I2C_CTRL);
+}
+
+static u32 i2c_indirect_read(struct altera_i2c_dev *dev, u32 reg)
+{
+	u64 tmp;
+	u64 ctrl;
+	u32 value;
+
+	ctrl = I2C_CTRL_R | (reg >> 2);
+	opae_writeq(ctrl, dev->base + I2C_CTRL);
+
+	/* FIXME: Read one more time to avoid HW timing issue. */
+	tmp = opae_readq(dev->base + I2C_READ);
+	tmp = opae_readq(dev->base + I2C_READ);
+
+	value = tmp & I2C_READ_DATA_MASK;
+
+	return value;
+}
+
+static void altera_i2c_transfer(struct altera_i2c_dev *dev, u32 data)
+{
+	/*send STOP on last byte*/
+	if (dev->msg_len == 1)
+		data |= ALTERA_I2C_TFR_CMD_STO;
+	if (dev->msg_len > 0)
+		i2c_indirect_write(dev, ALTERA_I2C_TFR_CMD, data);
+}
+
+static void altera_i2c_disable(struct altera_i2c_dev *dev)
+{
+	u32 val = i2c_indirect_read(dev, ALTERA_I2C_CTRL);
+
+	i2c_indirect_write(dev, ALTERA_I2C_CTRL, val&~ALTERA_I2C_CTRL_EN);
+}
+
+static void altera_i2c_enable(struct altera_i2c_dev *dev)
+{
+	u32 val = i2c_indirect_read(dev, ALTERA_I2C_CTRL);
+
+	i2c_indirect_write(dev, ALTERA_I2C_CTRL, val | ALTERA_I2C_CTRL_EN);
+}
+
+static void altera_i2c_reset(struct altera_i2c_dev *dev)
+{
+	altera_i2c_disable(dev);
+	altera_i2c_enable(dev);
+}
+
+static int altera_i2c_wait_core_idle(struct altera_i2c_dev *dev)
+{
+	int retry = 0;
+
+	while (i2c_indirect_read(dev, ALTERA_I2C_STATUS)
+			& ALTERA_I2C_STAT_CORE) {
+		if (retry++ > ALTERA_I2C_TIMEOUT_US) {
+			dev_err(dev, "timeout: Core Status not IDLE...\n");
+			return -EBUSY;
+		}
+		udelay(1);
+	}
+
+	return 0;
+}
+
+static void altera_i2c_enable_interrupt(struct altera_i2c_dev *dev,
+		u32 mask, bool enable)
+{
+	u32 status;
+
+	status = i2c_indirect_read(dev, ALTERA_I2C_ISER);
+	if (enable)
+		dev->isr_mask = status | mask;
+	else
+		dev->isr_mask = status&~mask;
+
+	i2c_indirect_write(dev, ALTERA_I2C_ISER, dev->isr_mask);
+}
+
+static void altera_i2c_interrupt_clear(struct altera_i2c_dev *dev, u32 mask)
+{
+	u32 int_en;
+
+	int_en = i2c_indirect_read(dev, ALTERA_I2C_ISR);
+
+	i2c_indirect_write(dev, ALTERA_I2C_ISR, int_en | mask);
+}
+
+static void altera_i2c_read_rx_fifo(struct altera_i2c_dev *dev)
+{
+	size_t rx_avail;
+	size_t bytes;
+
+	rx_avail = i2c_indirect_read(dev, ALTERA_I2C_RX_FIFO_LVL);
+	bytes = min(rx_avail, dev->msg_len);
+
+	while (bytes-- > 0) {
+		*dev->buf++ = i2c_indirect_read(dev, ALTERA_I2C_RX_DATA);
+		dev->msg_len--;
+		altera_i2c_transfer(dev, 0);
+	}
+}
+
+static void altera_i2c_stop(struct altera_i2c_dev *dev)
+{
+	i2c_indirect_write(dev, ALTERA_I2C_TFR_CMD, ALTERA_I2C_TFR_CMD_STO);
+}
+
+static int altera_i2c_fill_tx_fifo(struct altera_i2c_dev *dev)
+{
+	size_t tx_avail;
+	int bytes;
+	int ret;
+
+	tx_avail = dev->fifo_size -
+		i2c_indirect_read(dev, ALTERA_I2C_TC_FIFO_LVL);
+	bytes = min(tx_avail, dev->msg_len);
+	ret = dev->msg_len - bytes;
+
+	while (bytes-- > 0) {
+		altera_i2c_transfer(dev, *dev->buf++);
+		dev->msg_len--;
+	}
+
+	return ret;
+}
+
+static u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
+{
+	return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
+}
+
+static int altera_i2c_wait_complete(struct altera_i2c_dev *dev,
+		u32 *status)
+{
+	int retry = 0;
+
+	while (!((*status = i2c_indirect_read(dev, ALTERA_I2C_ISR))
+				& dev->isr_mask)) {
+		if (retry++ > ALTERA_I2C_TIMEOUT_US)
+			return -EBUSY;
+
+		udelay(1000);
+	}
+
+	return 0;
+}
+
+static bool altera_handle_i2c_status(struct altera_i2c_dev *dev, u32 status)
+{
+	bool read, finish = false;
+	int ret;
+
+	read = (dev->msg->flags & I2C_M_RD) != 0;
+
+	if (status & ALTERA_I2C_ISR_ARB) {
+		altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISR_ARB);
+		dev->msg_err = -EAGAIN;
+		finish = true;
+	} else if (status & ALTERA_I2C_ISR_NACK) {
+		dev_debug(dev, "could not get ACK\n");
+		dev->msg_err = -ENXIO;
+		altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISR_NACK);
+		altera_i2c_stop(dev);
+		finish = true;
+	} else if (read && (status & ALTERA_I2C_ISR_RXOF)) {
+		/* RX FIFO Overflow */
+		altera_i2c_read_rx_fifo(dev);
+		altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISER_RXOF_EN);
+		altera_i2c_stop(dev);
+		dev_err(dev, "error: RX FIFO overflow\n");
+		finish = true;
+	} else if (read && (status & ALTERA_I2C_ISR_RXRDY)) {
+		altera_i2c_read_rx_fifo(dev);
+		altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISR_RXRDY);
+		if (!dev->msg_len)
+			finish = true;
+	} else if (!read && (status & ALTERA_I2C_ISR_TXRDY)) {
+		altera_i2c_interrupt_clear(dev, ALTERA_I2C_ISR_TXRDY);
+		if (dev->msg_len > 0)
+			altera_i2c_fill_tx_fifo(dev);
+		else
+			finish = true;
+	} else {
+		dev_err(dev, "unexpected status:0x%x\n", status);
+		altera_i2c_interrupt_clear(dev, ALTERA_I2C_ALL_IRQ);
+	}
+
+	if (finish) {
+		ret = altera_i2c_wait_core_idle(dev);
+		if (ret)
+			dev_err(dev, "message timeout\n");
+
+		altera_i2c_enable_interrupt(dev, ALTERA_I2C_ALL_IRQ, false);
+		altera_i2c_interrupt_clear(dev, ALTERA_I2C_ALL_IRQ);
+		dev_debug(dev, "message done\n");
+	}
+
+	return finish;
+}
+
+static bool altera_i2c_poll_status(struct altera_i2c_dev *dev)
+{
+	u32 status;
+	bool finish = false;
+	int i = 0;
+
+	do {
+		if (altera_i2c_wait_complete(dev, &status)) {
+			dev_err(dev, "altera i2c wait complete timeout, status=0x%x\n",
+					status);
+			return -EBUSY;
+		}
+
+		finish = altera_handle_i2c_status(dev, status);
+
+		if (i++ > I2C_XFER_RETRY)
+			break;
+
+	} while (!finish);
+
+	return finish;
+}
+
+static int altera_i2c_xfer_msg(struct altera_i2c_dev *dev,
+		struct i2c_msg *msg)
+{
+	u32 int_mask = ALTERA_I2C_ISR_RXOF |
+		ALTERA_I2C_ISR_ARB | ALTERA_I2C_ISR_NACK;
+	u8 addr = i2c_8bit_addr_from_msg(msg);
+	bool finish;
+
+	dev->msg = msg;
+	dev->msg_len = msg->len;
+	dev->buf = msg->buf;
+	dev->msg_err = 0;
+	altera_i2c_enable(dev);
+
+	/*make sure RX FIFO is emtry*/
+	do {
+		i2c_indirect_read(dev, ALTERA_I2C_RX_DATA);
+	} while (i2c_indirect_read(dev, ALTERA_I2C_RX_FIFO_LVL));
+
+	i2c_indirect_write(dev, ALTERA_I2C_TFR_CMD_RW_D,
+			ALTERA_I2C_TFR_CMD_STA | addr);
+
+	/*enable irq*/
+	if (msg->flags & I2C_M_RD) {
+		int_mask |= ALTERA_I2C_ISR_RXOF | ALTERA_I2C_ISR_RXRDY;
+		/* in polling mode, we should set this ISR register? */
+		altera_i2c_enable_interrupt(dev, int_mask, true);
+		altera_i2c_transfer(dev, 0);
+	} else {
+		int_mask |= ALTERA_I2C_ISR_TXRDY;
+		altera_i2c_enable_interrupt(dev, int_mask, true);
+		altera_i2c_fill_tx_fifo(dev);
+	}
+
+	finish = altera_i2c_poll_status(dev);
+	if (!finish) {
+		dev->msg_err = -ETIMEDOUT;
+		dev_err(dev, "%s: i2c transfer error\n", __func__);
+	}
+
+	altera_i2c_enable_interrupt(dev, int_mask, false);
+
+	if (i2c_indirect_read(dev, ALTERA_I2C_STATUS) & ALTERA_I2C_STAT_CORE)
+		dev_info(dev, "core not idle...\n");
+
+	altera_i2c_disable(dev);
+
+	return dev->msg_err;
+}
+
+static int altera_i2c_xfer(struct altera_i2c_dev *dev,
+		struct i2c_msg *msg, int num)
+{
+	int ret = 0;
+	int i;
+
+	for (i = 0; i < num; i++, msg++) {
+		ret = altera_i2c_xfer_msg(dev, msg);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+static void altera_i2c_hardware_init(struct altera_i2c_dev *dev)
+{
+	u32 divisor = dev->i2c_clk / dev->bus_clk_rate;
+	u32 clk_mhz = dev->i2c_clk / 1000000;
+	u32 tmp = (ALTERA_I2C_THRESHOLD << ALTERA_I2C_CTRL_RXT_SHFT) |
+		  (ALTERA_I2C_THRESHOLD << ALTERA_I2C_CTRL_TCT_SHFT);
+	u32 t_high, t_low;
+
+	if (dev->bus_clk_rate <= 100000) {
+		tmp &= ~ALTERA_I2C_CTRL_BSPEED;
+		/*standard mode SCL 50/50*/
+		t_high = divisor*1/2;
+		t_low = divisor*1/2;
+	} else {
+		tmp |= ALTERA_I2C_CTRL_BSPEED;
+		/*Fast mode SCL 33/66*/
+		t_high = divisor*1/3;
+		t_low = divisor*2/3;
+	}
+
+	i2c_indirect_write(dev, ALTERA_I2C_CTRL, tmp);
+
+	dev_info(dev, "%s: rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
+		__func__, dev->bus_clk_rate, clk_mhz, divisor);
+
+	/*reset the i2c*/
+	altera_i2c_reset(dev);
+
+	/*Set SCL high Time*/
+	i2c_indirect_write(dev, ALTERA_I2C_SCL_HIGH, t_high);
+	/*Set SCL low time*/
+	i2c_indirect_write(dev, ALTERA_I2C_SCL_LOW, t_low);
+	/*Set SDA Hold time, 300ms*/
+	i2c_indirect_write(dev, ALTERA_I2C_SDA_HOLD, (300*clk_mhz)/1000);
+
+	altera_i2c_enable_interrupt(dev, ALTERA_I2C_ALL_IRQ, false);
+}
+
+struct altera_i2c_dev *altera_i2c_probe(void *base)
+{
+	struct altera_i2c_dev *dev;
+
+	dev = opae_malloc(sizeof(*dev));
+	if (!dev)
+		return NULL;
+
+	dev->base = (u8 *)base;
+	dev->i2c_param.info = opae_readq(dev->base + I2C_PARAM);
+
+	if (dev->i2c_param.devid != 0xEE011) {
+		dev_err(dev, "find a invalid i2c master\n");
+		return NULL;
+	}
+
+	dev->fifo_size = dev->i2c_param.fifo_depth;
+
+	if (dev->i2c_param.max_req == ALTERA_I2C_100KHZ)
+		dev->bus_clk_rate = 100000;
+	else if (dev->i2c_param.max_req == ALTERA_I2C_400KHZ)
+		/* i2c bus clk 400KHz*/
+		dev->bus_clk_rate = 400000;
+
+	/* i2c input clock for vista creek is 100MHz */
+	dev->i2c_clk = dev->i2c_param.ref_clk * 1000000;
+	dev->xfer = altera_i2c_xfer;
+
+	altera_i2c_hardware_init(dev);
+
+	return dev;
+}
+
+int altera_i2c_remove(struct altera_i2c_dev *dev)
+{
+	altera_i2c_disable(dev);
+
+	return 0;
+}
diff --git a/drivers/raw/ifpga_rawdev/base/opae_i2c.h b/drivers/raw/ifpga_rawdev/base/opae_i2c.h
new file mode 100644
index 0000000..8890c8f
--- /dev/null
+++ b/drivers/raw/ifpga_rawdev/base/opae_i2c.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2010-2019 Intel Corporation
+ */
+
+#ifndef _OPAE_I2C_H
+#define _OPAE_I2C_H
+
+#include "opae_osdep.h"
+
+#define ALTERA_I2C_TFR_CMD	0x00	/* Transfer Command register */
+#define ALTERA_I2C_TFR_CMD_STA	BIT(9)	/* send START before byte */
+#define ALTERA_I2C_TFR_CMD_STO	BIT(8)	/* send STOP after byte */
+#define ALTERA_I2C_TFR_CMD_RW_D	BIT(0)	/* Direction of transfer */
+#define ALTERA_I2C_RX_DATA	0x04	/* RX data FIFO register */
+#define ALTERA_I2C_CTRL		0x8	/* Control register */
+#define ALTERA_I2C_CTRL_RXT_SHFT	4	/* RX FIFO Threshold */
+#define ALTERA_I2C_CTRL_TCT_SHFT	2	/* TFER CMD FIFO Threshold */
+#define ALTERA_I2C_CTRL_BSPEED	BIT(1)	/* Bus Speed */
+#define ALTERA_I2C_CTRL_EN	BIT(0)	/* Enable Core */
+#define ALTERA_I2C_ISER		0xc	/* Interrupt Status Enable register */
+#define ALTERA_I2C_ISER_RXOF_EN	BIT(4)	/* Enable RX OVERFLOW IRQ */
+#define ALTERA_I2C_ISER_ARB_EN	BIT(3)	/* Enable ARB LOST IRQ */
+#define ALTERA_I2C_ISER_NACK_EN	BIT(2)	/* Enable NACK DET IRQ */
+#define ALTERA_I2C_ISER_RXRDY_EN	BIT(1)	/* Enable RX Ready IRQ */
+#define ALTERA_I2C_ISER_TXRDY_EN	BIT(0)	/* Enable TX Ready IRQ */
+#define ALTERA_I2C_ISR		0x10	/* Interrupt Status register */
+#define ALTERA_I2C_ISR_RXOF		BIT(4)	/* RX OVERFLOW */
+#define ALTERA_I2C_ISR_ARB		BIT(3)	/* ARB LOST */
+#define ALTERA_I2C_ISR_NACK		BIT(2)	/* NACK DET */
+#define ALTERA_I2C_ISR_RXRDY		BIT(1)	/* RX Ready */
+#define ALTERA_I2C_ISR_TXRDY		BIT(0)	/* TX Ready */
+#define ALTERA_I2C_STATUS	0x14	/* Status register */
+#define ALTERA_I2C_STAT_CORE		BIT(0)	/* Core Status */
+#define ALTERA_I2C_TC_FIFO_LVL	0x18   /* Transfer FIFO LVL register */
+#define ALTERA_I2C_RX_FIFO_LVL	0x1c	/* Receive FIFO LVL register */
+#define ALTERA_I2C_SCL_LOW	0x20	/* SCL low count register */
+#define ALTERA_I2C_SCL_HIGH	0x24	/* SCL high count register */
+#define ALTERA_I2C_SDA_HOLD	0x28	/* SDA hold count register */
+
+#define ALTERA_I2C_ALL_IRQ	(ALTERA_I2C_ISR_RXOF | ALTERA_I2C_ISR_ARB | \
+				 ALTERA_I2C_ISR_NACK | ALTERA_I2C_ISR_RXRDY | \
+				 ALTERA_I2C_ISR_TXRDY)
+
+#define ALTERA_I2C_THRESHOLD	0
+#define ALTERA_I2C_DFLT_FIFO_SZ	8
+#define ALTERA_I2C_TIMEOUT_US  250000 /* 250ms */
+
+#define I2C_PARAM 0x8
+#define I2C_CTRL  0x10
+#define I2C_CTRL_R    BIT_ULL(9)
+#define I2C_CTRL_W    BIT_ULL(8)
+#define I2C_CTRL_ADDR_MASK GENMASK_ULL(3, 0)
+#define I2C_READ 0x18
+#define I2C_READ_DATA_VALID BIT_ULL(32)
+#define I2C_READ_DATA_MASK GENMASK_ULL(31, 0)
+#define I2C_WRITE 0x20
+#define I2C_WRITE_DATA_MASK GENMASK_ULL(31, 0)
+
+#define ALTERA_I2C_100KHZ  0
+#define ALTERA_I2C_400KHZ  1
+
+/* i2c slave using 16bit address */
+#define I2C_FLAG_ADDR16  1
+
+#define I2C_XFER_RETRY 10
+
+struct i2c_core_param {
+	union {
+		u64 info;
+		struct {
+			u16 fifo_depth:9;
+			u8 interface:1;
+			/*reference clock of I2C core in MHz*/
+			u32 ref_clk:10;
+			/*Max I2C interface freq*/
+			u8 max_req:4;
+			u64 devid:32;
+			/* number of MAC address*/
+			u8 nu_macs:8;
+		};
+	};
+};
+
+struct altera_i2c_dev {
+	u8 *base;
+	struct i2c_core_param i2c_param;
+	u32 fifo_size;
+	u32 bus_clk_rate; /* i2c bus clock */
+	u32 i2c_clk; /* i2c input clock */
+	struct i2c_msg *msg;
+	size_t msg_len;
+	int msg_err;
+	u32 isr_mask;
+	u8 *buf;
+	int (*xfer)(struct altera_i2c_dev *dev, struct i2c_msg *msg, int num);
+};
+
+/**
+ * struct i2c_msg: an I2C message
+ */
+struct i2c_msg {
+	unsigned int addr;
+	unsigned int flags;
+	unsigned int len;
+	u8 *buf;
+};
+
+#define I2C_MAX_OFFSET_LEN 4
+
+enum i2c_msg_flags {
+	I2C_M_TEN = 0x0010, /*ten-bit chip address*/
+	I2C_M_RD  = 0x0001, /*read data*/
+	I2C_M_STOP = 0x8000, /*send stop after this message*/
+};
+
+struct altera_i2c_dev *altera_i2c_probe(void *base);
+int altera_i2c_remove(struct altera_i2c_dev *dev);
+int i2c_read(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
+		u32 offset, u8 *buf, u32 count);
+int i2c_write(struct altera_i2c_dev *dev, int flags, unsigned int slave_addr,
+		u32 offset, u8 *buffer, int len);
+int i2c_read8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
+		u8 *buf, u32 count);
+int i2c_read16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
+		u8 *buf, u32 count);
+int i2c_write8(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
+		u8 *buf, u32 count);
+int i2c_write16(struct altera_i2c_dev *dev, unsigned int slave_addr, u32 offset,
+		u8 *buf, u32 count);
+#endif
