diff mbox series

[v3,4/4] test: fix memory barrier test failure on power CPUs

Message ID 1557349363-26213-1-git-send-email-drc@linux.vnet.ibm.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series [v3,1/4] test: fix typo in print statement |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

David Christensen May 8, 2019, 9:02 p.m. UTC 
  The memory barrier test fails on IBM Power 9 systems.  Add additional
barriers to accommodate the weakly ordered model used on Power CPUs.

Signed-off-by: David Christensen <drc@linux.vnet.ibm.com>
---
v2:
* Removed ifdef's for PPC since the rte_smp_*mb() macros are already
  customized for each CPU architecture
v3:
* None
---
 app/test/test_barrier.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/app/test/test_barrier.c b/app/test/test_barrier.c
index a0b4704..43b5f62 100644
--- a/app/test/test_barrier.c
+++ b/app/test/test_barrier.c
@@ -92,12 +92,14 @@  struct lcore_plock_test {
 	other = self ^ 1;
 
 	l->flag[self] = 1;
+	rte_smp_wmb();
 	l->victim = self;
 
 	store_load_barrier(l->utype);
 
 	while (l->flag[other] == 1 && l->victim == self)
 		rte_pause();
+	rte_smp_rmb();
 }
 
 static void