From patchwork Thu Jun 6 17:33:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Rybchenko X-Patchwork-Id: 54516 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 62DA21B997; Thu, 6 Jun 2019 19:33:38 +0200 (CEST) Received: from dispatch1-us1.ppe-hosted.com (dispatch1-us1.ppe-hosted.com [67.231.154.164]) by dpdk.org (Postfix) with ESMTP id B4ADA1B94E for ; Thu, 6 Jun 2019 19:33:34 +0200 (CEST) X-Virus-Scanned: Proofpoint Essentials engine Received: from webmail.solarflare.com (webmail.solarflare.com [12.187.104.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by mx1-us4.ppe-hosted.com (PPE Hosted ESMTP Server) with ESMTPS id DFF07B400EA; Thu, 6 Jun 2019 17:33:32 +0000 (UTC) Received: from ocex03.SolarFlarecom.com (10.20.40.36) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 6 Jun 2019 10:33:30 -0700 Received: from opal.uk.solarflarecom.com (10.17.10.1) by ocex03.SolarFlarecom.com (10.20.40.36) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 6 Jun 2019 10:33:30 -0700 Received: from ukv-loginhost.uk.solarflarecom.com (ukv-loginhost.uk.solarflarecom.com [10.17.10.39]) by opal.uk.solarflarecom.com (8.13.8/8.13.8) with ESMTP id x56HXSbr017526; Thu, 6 Jun 2019 18:33:28 +0100 Received: from ukv-loginhost.uk.solarflarecom.com (localhost [127.0.0.1]) by ukv-loginhost.uk.solarflarecom.com (Postfix) with ESMTP id B5F7A1616E0; Thu, 6 Jun 2019 18:33:28 +0100 (BST) From: Andrew Rybchenko To: CC: Georgiy Levashov Date: Thu, 6 Jun 2019 18:33:25 +0100 Message-ID: <1559842405-7987-2-git-send-email-arybchenko@solarflare.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1559842405-7987-1-git-send-email-arybchenko@solarflare.com> References: <1559842405-7987-1-git-send-email-arybchenko@solarflare.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.5.0.1300-8.5.1010-24660.005 X-TM-AS-Result: No-3.742200-4.000000-10 X-TMASE-MatchedRID: TuwRzrPxPxY2jeY+Udg/IqiUivh0j2Pv6VTG9cZxEjIGmHr1eMxt2VMe 5Blkpry7rdoLblq9S5ra/g/NGTW3MnBgpI59xlp2LIrMljt3aduZ2scyRQcer3TcRTxyvO5LQlf mKk5XlH3mGdseOJ1P3iyiWj+fjuL0SVXlcVANHXbJ1E/nrJFEDxlKjo8zguyKBCzD0Dc8iUu6o5 pOE3X0ptu9HSeKDBZ/hnl/iEjUzwbym6NE9KB2dihJ5tvbfbyLD+jls0cSwJNIyDY579vwTNejy K9h2FCxonRtUk/HslhKcNiAgNXHNCoecX8cNVOhY/9H2iDo8CVDIUdcYoS0g5soi2XrUn/Jn6Kd MrRsL14qtq5d3cxkNY3CqpsRtoaOLJo/NlTIt2qUkQmjBjo02ZtKF6T2XhTVASGd9HFaz0sfO34 WZPljk7Z2CpOWaAsE7RRCgnxySPh0qj5Sqhgwh1X2XWozwhwOOKBkFAm8GOUPoO5ncI6OuehbQ2 QpmASdbcuA3Id6O6JDDKa3G4nrLQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.742200-4.000000 X-TMASE-Version: SMEX-12.5.0.1300-8.5.1010-24660.005 X-MDID: 1559842413-k3xlK2mKhenn Subject: [dpdk-dev] [PATCH 2/2] net/sfc: add Rx interrupts support for ef10 datapath X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Georgiy Levashov Similar to support for efx datapath, Rx interrupt disabling just avoids rearming the next time. Signed-off-by: Georgiy Levashov Signed-off-by: Andrew Rybchenko --- drivers/net/sfc/sfc_ef10.h | 12 +++++++++++ drivers/net/sfc/sfc_ef10_rx.c | 48 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/drivers/net/sfc/sfc_ef10.h b/drivers/net/sfc/sfc_ef10.h index a73e0bd..deb134d 100644 --- a/drivers/net/sfc/sfc_ef10.h +++ b/drivers/net/sfc/sfc_ef10.h @@ -109,6 +109,18 @@ rte_write32(dword.ed_u32[0], doorbell); } +static inline void +sfc_ef10_ev_qprime(volatile void *qprime, unsigned int read_ptr, + unsigned int ptr_mask) +{ + efx_dword_t dword; + + EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, read_ptr & ptr_mask); + + rte_write32_relaxed(dword.ed_u32[0], qprime); + rte_wmb(); +} + const uint32_t * sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps); diff --git a/drivers/net/sfc/sfc_ef10_rx.c b/drivers/net/sfc/sfc_ef10_rx.c index b294b43..f2fc6e7 100644 --- a/drivers/net/sfc/sfc_ef10_rx.c +++ b/drivers/net/sfc/sfc_ef10_rx.c @@ -56,14 +56,17 @@ struct sfc_ef10_rxq { #define SFC_EF10_RXQ_NOT_RUNNING 0x2 #define SFC_EF10_RXQ_EXCEPTION 0x4 #define SFC_EF10_RXQ_RSS_HASH 0x8 +#define SFC_EF10_RXQ_FLAG_INTR_EN 0x10 unsigned int ptr_mask; unsigned int pending; unsigned int completed; unsigned int evq_read_ptr; + unsigned int evq_read_ptr_primed; efx_qword_t *evq_hw_ring; struct sfc_ef10_rx_sw_desc *sw_ring; uint64_t rearm_data; struct rte_mbuf *scatter_pkt; + volatile void *evq_prime; uint16_t prefix_size; /* Used on refill */ @@ -86,6 +89,13 @@ struct sfc_ef10_rxq { } static void +sfc_ef10_rx_qprime(struct sfc_ef10_rxq *rxq) +{ + sfc_ef10_ev_qprime(rxq->evq_prime, rxq->evq_read_ptr, rxq->ptr_mask); + rxq->evq_read_ptr_primed = rxq->evq_read_ptr; +} + +static void sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq) { const unsigned int ptr_mask = rxq->ptr_mask; @@ -436,6 +446,10 @@ struct sfc_ef10_rxq { /* It is not a problem if we refill in the case of exception */ sfc_ef10_rx_qrefill(rxq); + if ((rxq->flags & SFC_EF10_RXQ_FLAG_INTR_EN) && + rxq->evq_read_ptr_primed != rxq->evq_read_ptr) + sfc_ef10_rx_qprime(rxq); + done: return nb_pkts - (rx_pkts_end - rx_pkts); } @@ -653,6 +667,9 @@ struct sfc_ef10_rxq { rxq->doorbell = (volatile uint8_t *)info->mem_bar + ER_DZ_RX_DESC_UPD_REG_OFST + (info->hw_index << info->vi_window_shift); + rxq->evq_prime = (volatile uint8_t *)info->mem_bar + + ER_DZ_EVQ_RPTR_REG_OFST + + (info->evq_hw_index << info->vi_window_shift); *dp_rxqp = &rxq->dp; return 0; @@ -692,6 +709,9 @@ struct sfc_ef10_rxq { rxq->flags |= SFC_EF10_RXQ_STARTED; rxq->flags &= ~(SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION); + if (rxq->flags & SFC_EF10_RXQ_FLAG_INTR_EN) + sfc_ef10_rx_qprime(rxq); + return 0; } @@ -744,13 +764,37 @@ struct sfc_ef10_rxq { rxq->flags &= ~SFC_EF10_RXQ_STARTED; } +static sfc_dp_rx_intr_enable_t sfc_ef10_rx_intr_enable; +static int +sfc_ef10_rx_intr_enable(struct sfc_dp_rxq *dp_rxq) +{ + struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq); + + rxq->flags |= SFC_EF10_RXQ_FLAG_INTR_EN; + if (rxq->flags & SFC_EF10_RXQ_STARTED) + sfc_ef10_rx_qprime(rxq); + return 0; +} + +static sfc_dp_rx_intr_disable_t sfc_ef10_rx_intr_disable; +static int +sfc_ef10_rx_intr_disable(struct sfc_dp_rxq *dp_rxq) +{ + struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq); + + /* Cannot disarm, just disable rearm */ + rxq->flags &= ~SFC_EF10_RXQ_FLAG_INTR_EN; + return 0; +} + struct sfc_dp_rx sfc_ef10_rx = { .dp = { .name = SFC_KVARG_DATAPATH_EF10, .type = SFC_DP_RX, .hw_fw_caps = SFC_DP_HW_FW_CAP_EF10, }, - .features = SFC_DP_RX_FEAT_MULTI_PROCESS, + .features = SFC_DP_RX_FEAT_MULTI_PROCESS | + SFC_DP_RX_FEAT_INTR, .dev_offload_capa = DEV_RX_OFFLOAD_CHECKSUM | DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, .queue_offload_capa = DEV_RX_OFFLOAD_SCATTER, @@ -765,5 +809,7 @@ struct sfc_dp_rx sfc_ef10_rx = { .supported_ptypes_get = sfc_ef10_supported_ptypes_get, .qdesc_npending = sfc_ef10_rx_qdesc_npending, .qdesc_status = sfc_ef10_rx_qdesc_status, + .intr_enable = sfc_ef10_rx_intr_enable, + .intr_disable = sfc_ef10_rx_intr_disable, .pkt_burst = sfc_ef10_recv_pkts, };