From patchwork Tue Jul 16 03:59:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ziyang Xuan X-Patchwork-Id: 56468 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C6AF92C18; Tue, 16 Jul 2019 05:46:30 +0200 (CEST) Received: from huawei.com (szxga06-in.huawei.com [45.249.212.32]) by dpdk.org (Postfix) with ESMTP id 70B962BF5 for ; Tue, 16 Jul 2019 05:46:29 +0200 (CEST) Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id C3AEC9E5E771BDB03D95 for ; Tue, 16 Jul 2019 11:46:26 +0800 (CST) Received: from tester.localdomain (10.175.119.39) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.439.0; Tue, 16 Jul 2019 11:46:19 +0800 From: Ziyang Xuan To: CC: , , , , , , Ziyang Xuan Date: Tue, 16 Jul 2019 11:59:28 +0800 Message-ID: <1563249568-35436-1-git-send-email-xuanziyang2@huawei.com> X-Mailer: git-send-email 1.8.3.1 MIME-Version: 1.0 X-Originating-IP: [10.175.119.39] X-CFilter-Loop: Reflected Subject: [dpdk-dev] [PATCH v1 1/1] net/hinic: solve lgtm errors reporting X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There are some implicit downcast errors in TX offload information parsing. This patch is to solve these errors. Signed-off-by: Ziyang Xuan --- drivers/net/hinic/hinic_pmd_tx.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/hinic/hinic_pmd_tx.h b/drivers/net/hinic/hinic_pmd_tx.h index 8b361cf..8a3df27 100644 --- a/drivers/net/hinic/hinic_pmd_tx.h +++ b/drivers/net/hinic/hinic_pmd_tx.h @@ -29,19 +29,20 @@ enum sq_wqe_type { struct hinic_tx_offload_info { u8 outer_l2_len; u8 outer_l3_type; - u8 outer_l3_len; + u16 outer_l3_len; u8 inner_l2_len; u8 inner_l3_type; - u8 inner_l3_len; + u16 inner_l3_len; u8 tunnel_length; u8 tunnel_type; u8 inner_l4_type; u8 inner_l4_len; - u8 payload_offset; + u16 payload_offset; u8 inner_l4_tcp_udp; + u8 rsvd0; }; /* tx sge info */