diff --git a/config/common_base b/config/common_base
index 8ef75c2..b8143ea 100644
--- a/config/common_base
+++ b/config/common_base
@@ -593,6 +593,11 @@ CONFIG_RTE_LIBRTE_DPAA_MAX_CRYPTODEV=4
 CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO=y
 
 #
+# Compile PMD for Marvell OCTEON TX2 crypto device
+#
+CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO=y
+
+#
 # Compile PMD for QuickAssist based devices - see docs for details
 #
 CONFIG_RTE_LIBRTE_PMD_QAT=y
diff --git a/drivers/common/Makefile b/drivers/common/Makefile
index bc6f972..1ff033b 100644
--- a/drivers/common/Makefile
+++ b/drivers/common/Makefile
@@ -4,7 +4,9 @@
 
 include $(RTE_SDK)/mk/rte.vars.mk
 
-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)
+CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
+ifneq (,$(findstring y,$(CPT-y)))
 DIRS-y += cpt
 endif
 
@@ -12,6 +14,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
 DIRS-y += octeontx
 endif
 OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)
+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
 ifeq ($(findstring y,$(OCTEONTX2-y)),y)
 DIRS-y += octeontx2
 endif
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 009f844..0ac999c 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -8,6 +8,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_AESNI_MB) += aesni_mb
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO) += armv8
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += octeontx
+DIRS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += octeontx2
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_OPENSSL) += openssl
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += scheduler
 DIRS-$(CONFIG_RTE_LIBRTE_PMD_SNOW3G) += snow3g
diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build
index 83e7886..3c88f3c 100644
--- a/drivers/crypto/meson.build
+++ b/drivers/crypto/meson.build
@@ -2,8 +2,8 @@
 # Copyright(c) 2017 Intel Corporation
 
 drivers = ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2_sec',
-	'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler',
-	'snow3g', 'virtio', 'zuc']
+	'kasumi', 'mvsam', 'null', 'octeontx', 'octeontx2', 'openssl', 'qat',
+	'scheduler', 'snow3g', 'virtio', 'zuc']
 
 std_deps = ['cryptodev'] # cryptodev pulls in all other needed deps
 config_flag_fmt = 'RTE_LIBRTE_@0@_PMD'
diff --git a/drivers/crypto/octeontx2/Makefile b/drivers/crypto/octeontx2/Makefile
new file mode 100644
index 0000000..3273178
--- /dev/null
+++ b/drivers/crypto/octeontx2/Makefile
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2019 Marvell International Ltd.
+#
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+# library name
+LIB = librte_pmd_octeontx2_crypto.a
+
+# library version
+LIBABIVER := 1
+
+# build flags
+CFLAGS += $(WERROR_FLAGS)
+
+LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring
+LDLIBS += -lrte_cryptodev
+LDLIBS += -lrte_pci -lrte_bus_pci
+LDLIBS += -lrte_common_cpt -lrte_common_octeontx2
+
+VPATH += $(RTE_SDK)/drivers/crypto/octeontx2
+
+CFLAGS += -O3
+CFLAGS += -I$(RTE_SDK)/drivers/common/cpt
+CFLAGS += -I$(RTE_SDK)/drivers/common/octeontx2
+
+# PMD code
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev.c
+SRCS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += otx2_cryptodev_ops.c
+
+# export include files
+SYMLINK-y-include +=
+
+# versioning export map
+EXPORT_MAP := rte_pmd_octeontx2_crypto_version.map
+
+include $(RTE_SDK)/mk/rte.lib.mk
diff --git a/drivers/crypto/octeontx2/meson.build b/drivers/crypto/octeontx2/meson.build
new file mode 100644
index 0000000..2b55d2a
--- /dev/null
+++ b/drivers/crypto/octeontx2/meson.build
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (C) 2019 Marvell International Ltd.
+
+if host_machine.system() != 'linux'
+        build = false
+endif
+
+deps += ['bus_pci']
+deps += ['common_cpt']
+deps += ['common_octeontx2']
+name = 'octeontx2_crypto'
+
+sources = files('otx2_cryptodev.c',
+		'otx2_cryptodev_ops.c')
+
+extra_flags = []
+# This integrated controller runs only on a arm64 machine, remove 32bit warnings
+if not dpdk_conf.get('RTE_ARCH_64')
+	extra_flags += ['-Wno-int-to-pointer-cast', '-Wno-pointer-to-int-cast']
+endif
+
+foreach flag: extra_flags
+	if cc.has_argument(flag)
+		cflags += flag
+	endif
+endforeach
+
+includes += include_directories('../../common/cpt')
+includes += include_directories('../../common/octeontx2')
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c
new file mode 100644
index 0000000..cf3a010
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.c
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_crypto.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_dev.h>
+#include <rte_errno.h>
+#include <rte_mempool.h>
+#include <rte_pci.h>
+
+/* CPT common headers */
+#include "cpt_common.h"
+#include "cpt_pmd_logs.h"
+
+#include "otx2_common.h"
+#include "otx2_cryptodev.h"
+#include "otx2_cryptodev_ops.h"
+
+static int otx2_cryptodev_logtype;
+
+static struct rte_pci_id pci_id_cpt_table[] = {
+	{
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+			       PCI_DEVID_OCTEONTX2_RVU_CPT_VF)
+	},
+	/* sentinel */
+	{
+		.device_id = 0
+	},
+};
+
+static int
+otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
+		   struct rte_pci_device *pci_dev)
+{
+	struct rte_cryptodev_pmd_init_params init_params = {
+		.name = "",
+		.socket_id = rte_socket_id(),
+		.private_data_size = sizeof(struct otx2_cpt_vf)
+	};
+	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+	struct rte_cryptodev *dev;
+	int ret;
+
+	/* Initialize logtype used in common */
+	cpt_logtype = otx2_cryptodev_logtype;
+
+	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+	dev = rte_cryptodev_pmd_create(name, &pci_dev->device, &init_params);
+	if (dev == NULL) {
+		ret = -ENODEV;
+		goto exit;
+	}
+
+	dev->dev_ops = &otx2_cpt_ops;
+
+	dev->driver_id = otx2_cryptodev_driver_id;
+
+	dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO |
+			     RTE_CRYPTODEV_FF_HW_ACCELERATED |
+			     RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING |
+			     RTE_CRYPTODEV_FF_IN_PLACE_SGL |
+			     RTE_CRYPTODEV_FF_OOP_SGL_IN_LB_OUT |
+			     RTE_CRYPTODEV_FF_OOP_SGL_IN_SGL_OUT;
+
+	return 0;
+
+exit:
+	CPT_LOG_ERR("Could not create device (vendor_id: 0x%x device_id: 0x%x)",
+		    pci_dev->id.vendor_id, pci_dev->id.device_id);
+	return ret;
+}
+
+static int
+otx2_cpt_pci_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_CRYPTODEV_NAME_MAX_LEN];
+	struct rte_cryptodev *dev;
+
+	if (pci_dev == NULL)
+		return -EINVAL;
+
+	rte_pci_device_name(&pci_dev->addr, name, sizeof(name));
+
+	dev = rte_cryptodev_pmd_get_named_dev(name);
+	if (dev == NULL)
+		return -ENODEV;
+
+	return rte_cryptodev_pmd_destroy(dev);
+}
+
+static struct rte_pci_driver otx2_cryptodev_pmd = {
+	.id_table = pci_id_cpt_table,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+	.probe = otx2_cpt_pci_probe,
+	.remove = otx2_cpt_pci_remove,
+};
+
+static struct cryptodev_driver otx2_cryptodev_drv;
+
+RTE_INIT(otx2_cpt_init_log);
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_OCTEONTX2_PMD, otx2_cryptodev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_OCTEONTX2_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_CRYPTO_DRIVER(otx2_cryptodev_drv, otx2_cryptodev_pmd.driver,
+		otx2_cryptodev_driver_id);
+
+RTE_INIT(otx2_cpt_init_log)
+{
+	/* Bus level logs */
+	otx2_cryptodev_logtype = rte_log_register("pmd.crypto.octeontx2");
+	if (otx2_cryptodev_logtype >= 0)
+		rte_log_set_level(otx2_cryptodev_logtype, RTE_LOG_NOTICE);
+}
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h
new file mode 100644
index 0000000..da0f653
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_H_
+#define _OTX2_CRYPTODEV_H_
+
+#include "cpt_common.h"
+
+/* Marvell OCTEON TX2 Crypto PMD device name */
+#define CRYPTODEV_NAME_OCTEONTX2_PMD	crypto_octeontx2
+
+/**
+ * Device private data
+ */
+struct otx2_cpt_vf {
+	/* To be populated */
+};
+
+/*
+ * Crypto device driver ID
+ */
+uint8_t otx2_cryptodev_driver_id;
+
+#endif /* _OTX2_CRYPTODEV_H_ */
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
new file mode 100644
index 0000000..18ad470
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include <rte_cryptodev_pmd.h>
+
+#include "otx2_cryptodev_ops.h"
+
+struct rte_cryptodev_ops otx2_cpt_ops = {
+	/* Device control ops */
+	.dev_configure = NULL,
+	.dev_start = NULL,
+	.dev_stop = NULL,
+	.dev_close = NULL,
+	.dev_infos_get = NULL,
+
+	.stats_get = NULL,
+	.stats_reset = NULL,
+	.queue_pair_setup = NULL,
+	.queue_pair_release = NULL,
+	.queue_pair_count = NULL,
+
+	/* Symmetric crypto ops */
+	.sym_session_get_size = NULL,
+	.sym_session_configure = NULL,
+	.sym_session_clear = NULL,
+};
diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
new file mode 100644
index 0000000..545614e
--- /dev/null
+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#ifndef _OTX2_CRYPTODEV_OPS_H_
+#define _OTX2_CRYPTODEV_OPS_H_
+
+#include <rte_cryptodev_pmd.h>
+
+struct rte_cryptodev_ops otx2_cpt_ops;
+
+#endif /* _OTX2_CRYPTODEV_OPS_H_ */
diff --git a/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
new file mode 100644
index 0000000..9a61188
--- /dev/null
+++ b/drivers/crypto/octeontx2/rte_pmd_octeontx2_crypto_version.map
@@ -0,0 +1,4 @@
+DPDK_19.08 {
+
+	local: *;
+};
diff --git a/mk/rte.app.mk b/mk/rte.app.mk
index ba5c39e..f85e50e 100644
--- a/mk/rte.app.mk
+++ b/mk/rte.app.mk
@@ -101,7 +101,9 @@ ifeq ($(CONFIG_RTE_EXEC_ENV_LINUX),y)
 _LDLIBS-$(CONFIG_RTE_LIBRTE_KNI)            += -lrte_kni
 endif
 
-ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO),y)
+OTX-CPT-y := $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO)
+OTX-CPT-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
+ifeq ($(findstring y,$(OTX-CPT-y)),y)
 _LDLIBS-y += -lrte_common_cpt
 endif
 
@@ -109,6 +111,7 @@ ifeq ($(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_SSOVF)$(CONFIG_RTE_LIBRTE_OCTEONTX_MEMPOO
 _LDLIBS-y += -lrte_common_octeontx
 endif
 OCTEONTX2-y := $(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL)
+OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO)
 OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_EVENTDEV)
 OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_DMA_RAWDEV)
 OCTEONTX2-y += $(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD)
@@ -268,6 +271,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -lrte_pmd_armv8
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO)    += -L$(ARMV8_CRYPTO_LIB_PATH) -larmv8_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO) += -L$(LIBMUSDK_PATH)/lib -lrte_pmd_mvsam_crypto -lmusdk
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX_CRYPTO) += -lrte_pmd_octeontx_crypto
+_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_OCTEONTX2_CRYPTO) += -lrte_pmd_octeontx2_crypto
 _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER) += -lrte_pmd_crypto_scheduler
 ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y)
 ifeq ($(CONFIG_RTE_EAL_VFIO)$(CONFIG_RTE_LIBRTE_FSLMC_BUS),yy)
