[v17,4/8] eal/arm: update CPU flags
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Commit Message
There are two execution states on armv8 architecture, aarch64 and
aarch32. Add PLATFORM_STR for the latter and update RTE_ARCH_* flags
according to e9b97392640.
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
---
lib/eal/arm/include/rte_cpuflags_32.h | 1 +
lib/eal/arm/rte_cpuflags.c | 10 +++++++++-
2 files changed, 10 insertions(+), 1 deletion(-)
Comments
> -----Original Message-----
> From: Juraj Linkeš <juraj.linkes@pantheon.tech>
> Sent: Thursday, April 22, 2021 8:49 PM
> To: thomas@monjalon.net; david.marchand@redhat.com;
> bruce.richardson@intel.com; aconole@redhat.com;
> maicolgabriel@hotmail.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; Ruifeng Wang
> <Ruifeng.Wang@arm.com>; jerinj@marvell.com; viktorin@rehivetech.com;
> Ajit Khaparde (ajit.khaparde@broadcom.com)
> <ajit.khaparde@broadcom.com>
> Cc: juraj.linkes@pantheon.tech; dev@dpdk.org
> Subject: [PATCH v17 4/8] eal/arm: update CPU flags
>
> There are two execution states on armv8 architecture, aarch64 and aarch32.
> Add PLATFORM_STR for the latter and update RTE_ARCH_* flags according
> to e9b97392640.
>
> Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
> ---
> lib/eal/arm/include/rte_cpuflags_32.h | 1 +
> lib/eal/arm/rte_cpuflags.c | 10 +++++++++-
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/lib/eal/arm/include/rte_cpuflags_32.h
> b/lib/eal/arm/include/rte_cpuflags_32.h
> index b5347be1ec..4e254428a2 100644
> --- a/lib/eal/arm/include/rte_cpuflags_32.h
> +++ b/lib/eal/arm/include/rte_cpuflags_32.h
> @@ -41,6 +41,7 @@ enum rte_cpu_flag_t {
> RTE_CPUFLAG_SHA2,
> RTE_CPUFLAG_CRC32,
> RTE_CPUFLAG_V7L,
> + RTE_CPUFLAG_V8L,
> /* The last item */
> RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ };
> diff --git a/lib/eal/arm/rte_cpuflags.c b/lib/eal/arm/rte_cpuflags.c index
> e3a53bcece..9e5b68b066 100644
> --- a/lib/eal/arm/rte_cpuflags.c
> +++ b/lib/eal/arm/rte_cpuflags.c
> @@ -46,8 +46,12 @@ struct feature_entry { #define FEAT_DEF(name, reg,
> bit) \
> [RTE_CPUFLAG_##name] = {reg, bit, #name},
>
> +#ifdef RTE_ARCH_32
> #ifdef RTE_ARCH_ARMv7
> #define PLATFORM_STR "v7l"
> +#elif defined RTE_ARCH_ARMv8_AARCH32
> +#define PLATFORM_STR "v8l"
> +#endif
> typedef Elf32_auxv_t _Elfx_auxv_t;
>
> const struct feature_entry rte_cpu_feature_table[] = { @@ -78,10 +82,14
> @@ const struct feature_entry rte_cpu_feature_table[] = {
> FEAT_DEF(SHA1, REG_HWCAP2, 2)
> FEAT_DEF(SHA2, REG_HWCAP2, 3)
> FEAT_DEF(CRC32, REG_HWCAP2, 4)
> + #ifdef RTE_ARCH_ARMv7
> FEAT_DEF(V7L, REG_PLATFORM, 0)
> + #elif defined RTE_ARCH_ARMv8_AARCH32
> + FEAT_DEF(V8L, REG_PLATFORM, 0)
> + #endif
> };
>
> -#elif defined RTE_ARCH_ARM64
> +#elif defined RTE_ARCH_64
> #define PLATFORM_STR "aarch64"
> typedef Elf64_auxv_t _Elfx_auxv_t;
>
> --
> 2.20.1
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
@@ -41,6 +41,7 @@ enum rte_cpu_flag_t {
RTE_CPUFLAG_SHA2,
RTE_CPUFLAG_CRC32,
RTE_CPUFLAG_V7L,
+ RTE_CPUFLAG_V8L,
/* The last item */
RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
};
@@ -46,8 +46,12 @@ struct feature_entry {
#define FEAT_DEF(name, reg, bit) \
[RTE_CPUFLAG_##name] = {reg, bit, #name},
+#ifdef RTE_ARCH_32
#ifdef RTE_ARCH_ARMv7
#define PLATFORM_STR "v7l"
+#elif defined RTE_ARCH_ARMv8_AARCH32
+#define PLATFORM_STR "v8l"
+#endif
typedef Elf32_auxv_t _Elfx_auxv_t;
const struct feature_entry rte_cpu_feature_table[] = {
@@ -78,10 +82,14 @@ const struct feature_entry rte_cpu_feature_table[] = {
FEAT_DEF(SHA1, REG_HWCAP2, 2)
FEAT_DEF(SHA2, REG_HWCAP2, 3)
FEAT_DEF(CRC32, REG_HWCAP2, 4)
+ #ifdef RTE_ARCH_ARMv7
FEAT_DEF(V7L, REG_PLATFORM, 0)
+ #elif defined RTE_ARCH_ARMv8_AARCH32
+ FEAT_DEF(V8L, REG_PLATFORM, 0)
+ #endif
};
-#elif defined RTE_ARCH_ARM64
+#elif defined RTE_ARCH_64
#define PLATFORM_STR "aarch64"
typedef Elf64_auxv_t _Elfx_auxv_t;