From patchwork Thu May 26 00:55:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 111870 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B4F4A0548; Thu, 26 May 2022 03:05:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1B07242B70; Thu, 26 May 2022 03:04:34 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mails.dpdk.org (Postfix) with ESMTP id B77514067B for ; Thu, 26 May 2022 03:04:28 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653527068; x=1685063068; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Au7kZFWw0JDO0Vkbpr5Pt5sZO5IAvZyutLepp1zKKMI=; b=XakrsJQV7RyQZ+BSI+lwUQzbYNX7QiBVpGyz5GLiSi8fWjxkmwAP+3tB 7N5J7TnUNpLb0Nv+DciR71mq+oGXcPmePDo8lWOuG3H+xbx5cs47YR0k2 9cZJGJtLtdcLC8gxzTUmI+Abn0S/v83pqquy+93CzEn4vhA+LM830Ay78 YESgy7aK0Ly19NArlNV5C8mg+IUtAVswXrlpoRqYmYFnxcGMnyM/ayp/b 319vBugoUwFDZn6Zla6pLs1B9Wz9WCQIrIQksBbTC9YO5M58aq2tJkaka m9uXa6IFhVt6gjDZk9Jg2xvOX78HIe0bh+riLOUdS2actFsapWFsBHqdO A==; X-IronPort-AV: E=McAfee;i="6400,9594,10358"; a="274089460" X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="274089460" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 May 2022 18:04:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,252,1647327600"; d="scan'208";a="549294881" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by orsmga006.jf.intel.com with ESMTP; 25 May 2022 18:04:24 -0700 From: Nicolas Chautru To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com, hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com, Nicolas Chautru Subject: [PATCH v6 5/5] baseband/acc100: configuration of ACC101 from PF Date: Wed, 25 May 2022 17:55:23 -0700 Message-Id: <1653526523-68839-6-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> References: <1653350912-53876-1-git-send-email-nicolas.chautru@intel.com> <1653526523-68839-1-git-send-email-nicolas.chautru@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Adding companion function common to ACC100/ACC101 which can be called from bbdev-test when running from PF. Signed-off-by: Nicolas Chautru --- app/test-bbdev/test_bbdev_perf.c | 6 +- drivers/baseband/acc100/rte_acc100_cfg.h | 4 +- drivers/baseband/acc100/rte_acc100_pmd.c | 323 ++++++++++++++++++++++++++++++- drivers/baseband/acc100/version.map | 3 +- 4 files changed, 327 insertions(+), 9 deletions(-) diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index 0fa119a..718e5ef 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -711,11 +711,11 @@ typedef int (test_case_function)(struct active_device *ad, #endif #ifdef RTE_BASEBAND_ACC100 if ((get_init_device() == true) && - (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) { + (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) { struct rte_acc100_conf conf; unsigned int i; - printf("Configure ACC100 FEC Driver %s with default values\n", + printf("Configure ACC100/ACC101 FEC Driver %s with default values\n", info->drv.driver_name); /* clear default configuration before initialization */ @@ -760,7 +760,7 @@ typedef int (test_case_function)(struct active_device *ad, conf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH; /* setup PF with configuration information */ - ret = rte_acc100_configure(info->dev_name, &conf); + ret = rte_acc10x_configure(info->dev_name, &conf); TEST_ASSERT_SUCCESS(ret, "Failed to configure ACC100 PF for bbdev %s", info->dev_name); diff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h index d233e42..b70803d 100644 --- a/drivers/baseband/acc100/rte_acc100_cfg.h +++ b/drivers/baseband/acc100/rte_acc100_cfg.h @@ -90,7 +90,7 @@ struct rte_acc100_conf { }; /** - * Configure a ACC100 device + * Configure a ACC100/ACC101 device in PF mode notably for bbdev-test * * @param dev_name * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0. @@ -104,7 +104,7 @@ struct rte_acc100_conf { */ __rte_experimental int -rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf); +rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf); #ifdef __cplusplus } diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index a057edf..86545cc 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -4574,8 +4574,8 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) } /* Initial configuration of a ACC100 device prior to running configure() */ -int -rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf) +static int +acc100_configure(const char *dev_name, struct rte_acc100_conf *conf) { rte_bbdev_log(INFO, "rte_acc100_configure"); uint32_t value, address, status; @@ -4975,3 +4975,322 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev) rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name); return 0; } + + +/* Initial configuration of a ACC101 device prior to running configure() */ +static int +acc101_configure(const char *dev_name, struct rte_acc100_conf *conf) +{ + rte_bbdev_log(INFO, "rte_acc101_configure"); + uint32_t value, address, status; + int qg_idx, template_idx, vf_idx, acc, i; + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); + + /* Compile time checks */ + RTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256); + RTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256); + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24); + RTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32); + + if (bbdev == NULL) { + rte_bbdev_log(ERR, + "Invalid dev_name (%s), or device is not yet initialised", + dev_name); + return -ENODEV; + } + struct acc100_device *d = bbdev->data->dev_private; + + /* Store configuration */ + rte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf)); + + /* PCIe Bridge configuration */ + acc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE); + for (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++) + acc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0); + + /* Prevent blocking AXI read on BRESP for AXI Write */ + address = HwPfPcieGpexAxiPioControl; + value = ACC101_CFG_PCI_AXI; + acc100_reg_write(d, address, value); + + /* Explicitly releasing AXI including a 2ms delay on ACC101 */ + usleep(2000); + acc100_reg_write(d, HWPfDmaAxiControl, 1); + + /* Set the default 5GDL DMA configuration */ + acc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND); + + /* Enable granular dynamic clock gating */ + address = HWPfHiClkGateHystReg; + value = ACC101_CLOCK_GATING_EN; + acc100_reg_write(d, address, value); + + /* Set default descriptor signature */ + address = HWPfDmaDescriptorSignatuture; + value = 0; + acc100_reg_write(d, address, value); + + /* Enable the Error Detection in DMA */ + value = ACC101_CFG_DMA_ERROR; + address = HWPfDmaErrorDetectionEn; + acc100_reg_write(d, address, value); + + /* AXI Cache configuration */ + value = ACC101_CFG_AXI_CACHE; + address = HWPfDmaAxcacheReg; + acc100_reg_write(d, address, value); + + /* Default DMA Configuration (Qmgr Enabled) */ + address = HWPfDmaConfig0Reg; + value = 0; + acc100_reg_write(d, address, value); + address = HWPfDmaQmanen; + value = 0; + acc100_reg_write(d, address, value); + + /* Default RLIM/ALEN configuration */ + address = HWPfDmaConfig1Reg; + int alen_r = 0xF; + int alen_w = 0x7; + value = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r; + acc100_reg_write(d, address, value); + + /* Configure DMA Qmanager addresses */ + address = HWPfDmaQmgrAddrReg; + value = HWPfQmgrEgressQueuesTemplate; + acc100_reg_write(d, address, value); + + /* ===== Qmgr Configuration ===== */ + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */ + int totalQgs = conf->q_ul_4g.num_qgroups + + conf->q_ul_5g.num_qgroups + + conf->q_dl_4g.num_qgroups + + conf->q_dl_5g.num_qgroups; + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + address = HWPfQmgrDepthLog2Grp + + ACC101_BYTES_IN_WORD * qg_idx; + value = aqDepth(qg_idx, conf); + acc100_reg_write(d, address, value); + address = HWPfQmgrTholdGrp + + ACC101_BYTES_IN_WORD * qg_idx; + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1)); + acc100_reg_write(d, address, value); + } + + /* Template Priority in incremental order */ + for (template_idx = 0; template_idx < ACC101_NUM_TMPL; + template_idx++) { + address = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_0; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_1; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_2; + acc100_reg_write(d, address, value); + address = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx; + value = ACC101_TMPL_PRI_3; + acc100_reg_write(d, address, value); + } + + address = HWPfQmgrGrpPriority; + value = ACC101_CFG_QMGR_HI_P; + acc100_reg_write(d, address, value); + + /* Template Configuration */ + for (template_idx = 0; template_idx < ACC101_NUM_TMPL; + template_idx++) { + value = 0; + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); + } + /* 4GUL */ + int numQgs = conf->q_ul_4g.num_qgroups; + int numQqsAcc = 0; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_UL_4G; + template_idx <= ACC101_SIG_UL_4G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); + } + /* 5GUL */ + numQqsAcc += numQgs; + numQgs = conf->q_ul_5g.num_qgroups; + value = 0; + int numEngines = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_UL_5G; + template_idx <= ACC101_SIG_UL_5G_LAST; + template_idx++) { + /* Check engine power-on status */ + address = HwPfFecUl5gIbDebugReg + + ACC101_ENGINE_OFFSET * template_idx; + status = (acc100_reg_read(d, address) >> 4) & 0xF; + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + if (status == 1) { + acc100_reg_write(d, address, value); + numEngines++; + } else + acc100_reg_write(d, address, 0); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + printf("Number of 5GUL engines %d\n", numEngines); + /* 4GDL */ + numQqsAcc += numQgs; + numQgs = conf->q_dl_4g.num_qgroups; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_DL_4G; + template_idx <= ACC101_SIG_DL_4G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + /* 5GDL */ + numQqsAcc += numQgs; + numQgs = conf->q_dl_5g.num_qgroups; + value = 0; + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++) + value |= (1 << qg_idx); + for (template_idx = ACC101_SIG_DL_5G; + template_idx <= ACC101_SIG_DL_5G_LAST; + template_idx++) { + address = HWPfQmgrGrpTmplateReg4Indx + + ACC101_BYTES_IN_WORD * template_idx; + acc100_reg_write(d, address, value); +#if RTE_ACC101_SINGLE_FEC == 1 + value = 0; +#endif + } + + /* Queue Group Function mapping */ + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0}; + address = HWPfQmgrGrpFunction0; + value = 0; + for (qg_idx = 0; qg_idx < 8; qg_idx++) { + acc = accFromQgid(qg_idx, conf); + value |= qman_func_id[acc]<<(qg_idx * 4); + } + acc100_reg_write(d, address, value); + + /* Configuration of the Arbitration QGroup depth to 1 */ + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + address = HWPfQmgrArbQDepthGrp + + ACC101_BYTES_IN_WORD * qg_idx; + value = 0; + acc100_reg_write(d, address, value); + } + + /* Enabling AQueues through the Queue hierarchy*/ + for (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) { + for (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) { + value = 0; + if (vf_idx < conf->num_vf_bundles && + qg_idx < totalQgs) + value = (1 << aqNum(qg_idx, conf)) - 1; + address = HWPfQmgrAqEnableVf + + vf_idx * ACC101_BYTES_IN_WORD; + value += (qg_idx << 16); + acc100_reg_write(d, address, value); + } + } + + /* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */ + uint32_t aram_address = 0; + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) { + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { + address = HWPfQmgrVfBaseAddr + vf_idx + * ACC101_BYTES_IN_WORD + qg_idx + * ACC101_BYTES_IN_WORD * 64; + value = aram_address; + acc100_reg_write(d, address, value); + /* Offset ARAM Address for next memory bank + * - increment of 4B + */ + aram_address += aqNum(qg_idx, conf) * + (1 << aqDepth(qg_idx, conf)); + } + } + + if (aram_address > ACC101_WORDS_IN_ARAM_SIZE) { + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n", + aram_address, ACC101_WORDS_IN_ARAM_SIZE); + return -EINVAL; + } + + /* ==== HI Configuration ==== */ + + /* No Info Ring/MSI by default */ + acc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0); + acc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0); + acc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF); + acc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF); + /* Prevent Block on Transmit Error */ + address = HWPfHiBlockTransmitOnErrorEn; + value = 0; + acc100_reg_write(d, address, value); + /* Prevents to drop MSI */ + address = HWPfHiMsiDropEnableReg; + value = 0; + acc100_reg_write(d, address, value); + /* Set the PF Mode register */ + address = HWPfHiPfMode; + value = (conf->pf_mode_en) ? ACC101_PF_VAL : 0; + acc100_reg_write(d, address, value); + /* Explicitly releasing AXI after PF Mode and 2 ms */ + usleep(2000); + acc100_reg_write(d, HWPfDmaAxiControl, 1); + + /* QoS overflow init */ + value = 1; + address = HWPfQosmonAEvalOverflow0; + acc100_reg_write(d, address, value); + address = HWPfQosmonBEvalOverflow0; + acc100_reg_write(d, address, value); + + /* HARQ DDR Configuration */ + unsigned int ddrSizeInMb = ACC101_HARQ_DDR; + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) { + address = HWPfDmaVfDdrBaseRw + vf_idx + * 0x10; + value = ((vf_idx * (ddrSizeInMb / 64)) << 16) + + (ddrSizeInMb - 1); + acc100_reg_write(d, address, value); + } + usleep(ACC101_LONG_WAIT); + + rte_bbdev_log_debug("PF TIP configuration complete for %s", dev_name); + return 0; +} + +int +rte_acc10x_configure(const char *dev_name, struct rte_acc100_conf *conf) +{ + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); + if (bbdev == NULL) { + rte_bbdev_log(ERR, "Invalid dev_name (%s), or device is not yet initialised", + dev_name); + return -ENODEV; + } + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device); + printf("Configure dev id %x\n", pci_dev->id.device_id); + if (pci_dev->id.device_id == RTE_ACC100_PF_DEVICE_ID) + return acc100_configure(dev_name, conf); + else + return acc101_configure(dev_name, conf); +} diff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map index 40604c7..13f0398 100644 --- a/drivers/baseband/acc100/version.map +++ b/drivers/baseband/acc100/version.map @@ -5,6 +5,5 @@ DPDK_22 { EXPERIMENTAL { global: - rte_acc100_configure; - + rte_acc10x_configure; };