[v5,3/5] raw/afu_mf: add HE-LBK AFU driver
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Commit Message
HE-LBK and HE-MEM-LBK are host exerciser modules in OFS FPGA,
HE-LBK is used to test PCI bus and HE-MEM-LBK is used to test
local memory.
This driver initialize the modules and report test result.
Signed-off-by: Wei Huang <wei.huang@intel.com>
---
drivers/raw/afu_mf/afu_mf_rawdev.c | 5 +
drivers/raw/afu_mf/he_lbk.c | 427 +++++++++++++++++++++++++++++++++++++
drivers/raw/afu_mf/he_lbk.h | 121 +++++++++++
drivers/raw/afu_mf/meson.build | 2 +-
drivers/raw/afu_mf/rte_pmd_afu.h | 14 ++
5 files changed, 568 insertions(+), 1 deletion(-)
create mode 100644 drivers/raw/afu_mf/he_lbk.c
create mode 100644 drivers/raw/afu_mf/he_lbk.h
Comments
> -----Original Message-----
> From: Huang, Wei <wei.huang@intel.com>
> Sent: Friday, May 27, 2022 1:37 PM
> To: dev@dpdk.org; thomas@monjalon.net; nipun.gupta@nxp.com;
> hemant.agrawal@nxp.com
> Cc: stable@dpdk.org; Xu, Rosen <rosen.xu@intel.com>; Zhang, Tianfei
> <tianfei.zhang@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>; Huang, Wei
> <wei.huang@intel.com>
> Subject: [PATCH v5 3/5] raw/afu_mf: add HE-LBK AFU driver
>
> HE-LBK and HE-MEM-LBK are host exerciser modules in OFS FPGA, HE-LBK is
> used to test PCI bus and HE-MEM-LBK is used to test local memory.
> This driver initialize the modules and report test result.
>
> Signed-off-by: Wei Huang <wei.huang@intel.com>
> ---
> drivers/raw/afu_mf/afu_mf_rawdev.c | 5 +
> drivers/raw/afu_mf/he_lbk.c | 427
> +++++++++++++++++++++++++++++++++++++
> drivers/raw/afu_mf/he_lbk.h | 121 +++++++++++
> drivers/raw/afu_mf/meson.build | 2 +-
> drivers/raw/afu_mf/rte_pmd_afu.h | 14 ++
> 5 files changed, 568 insertions(+), 1 deletion(-) create mode 100644
> drivers/raw/afu_mf/he_lbk.c create mode 100644 drivers/raw/afu_mf/he_lbk.h
>
> diff --git a/drivers/raw/afu_mf/afu_mf_rawdev.c
> b/drivers/raw/afu_mf/afu_mf_rawdev.c
> index 7c18f3b..e91eb21 100644
> --- a/drivers/raw/afu_mf/afu_mf_rawdev.c
> +++ b/drivers/raw/afu_mf/afu_mf_rawdev.c
> @@ -20,16 +20,21 @@
> #include "rte_pmd_afu.h"
> #include "afu_mf_rawdev.h"
> #include "n3000_afu.h"
> +#include "he_lbk.h"
>
> #define AFU_MF_PMD_RAWDEV_NAME rawdev_afu_mf
>
> static const struct rte_afu_uuid afu_uuid_map[] = {
> { N3000_AFU_UUID_L, N3000_AFU_UUID_H },
> + { HE_LBK_UUID_L, HE_LBK_UUID_H },
> + { HE_MEM_LBK_UUID_L, HE_MEM_LBK_UUID_H },
> { 0, 0 /* sentinel */ }
> };
>
> static struct afu_mf_drv *afu_table[] = {
> &n3000_afu_drv,
> + &he_lbk_drv,
> + &he_mem_lbk_drv,
> NULL
> };
>
> diff --git a/drivers/raw/afu_mf/he_lbk.c b/drivers/raw/afu_mf/he_lbk.c new file
> mode 100644 index 0000000..8735647
> --- /dev/null
> +++ b/drivers/raw/afu_mf/he_lbk.c
> @@ -0,0 +1,427 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +#include <errno.h>
> +#include <stdio.h>
> +#include <stdint.h>
> +#include <stdlib.h>
> +#include <inttypes.h>
> +#include <unistd.h>
> +#include <fcntl.h>
> +#include <poll.h>
> +#include <sys/eventfd.h>
> +#include <sys/ioctl.h>
> +
> +#include <rte_eal.h>
> +#include <rte_malloc.h>
> +#include <rte_memcpy.h>
> +#include <rte_io.h>
> +#include <rte_vfio.h>
> +#include <rte_bus_pci.h>
> +#include <rte_bus_ifpga.h>
> +#include <rte_rawdev.h>
> +
> +#include "afu_mf_rawdev.h"
> +#include "he_lbk.h"
> +
> +static int he_lbk_afu_config(struct afu_mf_rawdev *dev) {
> + struct he_lbk_priv *priv = NULL;
> + struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
> + struct he_lbk_csr_cfg v;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + priv = (struct he_lbk_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + cfg = &priv->he_lbk_cfg;
> +
> + v.csr = 0;
> +
> + if (cfg->cont)
> + v.cont = 1;
> +
> + v.mode = cfg->mode;
> + v.trput_interleave = cfg->trput_interleave;
> + if (cfg->multi_cl == 4)
> + v.multicl_len = 2;
> + else
> + v.multicl_len = cfg->multi_cl - 1;
> +
> + AFU_MF_PMD_DEBUG("cfg: 0x%08x", v.csr);
> + rte_write32(v.csr, priv->he_lbk_ctx.addr + CSR_CFG);
> +
> + return 0;
> +}
> +
> +static void he_lbk_report(struct afu_mf_rawdev *dev, uint32_t cl) {
> + struct he_lbk_priv *priv = NULL;
> + struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
> + struct he_lbk_ctx *ctx = NULL;
> + struct he_lbk_dsm_status *stat = NULL;
> + struct he_lbk_status0 stat0;
> + struct he_lbk_status1 stat1;
> + uint64_t swtest_msg = 0;
> + uint64_t ticks = 0;
> + uint64_t info = 0;
> + double num, rd_bw, wr_bw;
> +
> + if (!dev || !dev->priv)
> + return;
> +
> + priv = (struct he_lbk_priv *)dev->priv;
> + cfg = &priv->he_lbk_cfg;
> + ctx = &priv->he_lbk_ctx;
> +
> + stat = ctx->status_ptr;
> +
> + swtest_msg = rte_read64(ctx->addr + CSR_SWTEST_MSG);
> + stat0.csr = rte_read64(ctx->addr + CSR_STATUS0);
> + stat1.csr = rte_read64(ctx->addr + CSR_STATUS1);
> +
> + if (cfg->cont)
> + ticks = stat->num_clocks - stat->start_overhead;
> + else
> + ticks = stat->num_clocks -
> + (stat->start_overhead + stat->end_overhead);
> +
> + if (cfg->freq_mhz == 0) {
> + info = rte_read64(ctx->addr + CSR_HE_INFO0);
> + AFU_MF_PMD_INFO("API version: %"PRIx64, info >> 16);
> + cfg->freq_mhz = info & 0xffff;
> + if (cfg->freq_mhz == 0) {
> + AFU_MF_PMD_INFO("Frequency of AFU clock is
> unknown."
> + " Assuming 350 MHz.");
> + cfg->freq_mhz = 350;
> + }
> + }
> +
> + num = (double)stat0.num_reads;
> + rd_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
> + num = (double)stat0.num_writes;
> + wr_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
> +
> + printf("Cachelines Read_Count Write_Count Pend_Read Pend_Write "
> + "Clocks@%uMHz Rd_Bandwidth Wr_Bandwidth\n",
> + cfg->freq_mhz);
> + printf("%10u %10u %10u %10u %10u %12"PRIu64
> + " %7.3f GB/s %7.3f GB/s\n",
> + cl, stat0.num_reads, stat0.num_writes,
> + stat1.num_pend_reads, stat1.num_pend_writes,
> + ticks, rd_bw / 1e9, wr_bw / 1e9);
> + printf("Test Message: 0x%"PRIx64"\n", swtest_msg); }
> +
> +static int he_lbk_test(struct afu_mf_rawdev *dev) {
> + struct he_lbk_priv *priv = NULL;
> + struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
> + struct he_lbk_ctx *ctx = NULL;
> + struct he_lbk_csr_ctl ctl;
> + uint32_t *ptr = NULL;
> + uint32_t i, j, cl, val = 0;
> + uint64_t sval = 0;
> + int ret = 0;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + priv = (struct he_lbk_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + cfg = &priv->he_lbk_cfg;
> + ctx = &priv->he_lbk_ctx;
> +
> + ctl.csr = 0;
> + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> + rte_delay_us(1000);
> + ctl.reset = 1;
> + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> +
> + /* initialize DMA addresses */
> + AFU_MF_PMD_DEBUG("src_addr: 0x%"PRIx64, ctx->src_iova);
> + rte_write64(SIZE_TO_CLS(ctx->src_iova), ctx->addr + CSR_SRC_ADDR);
> +
> + AFU_MF_PMD_DEBUG("dst_addr: 0x%"PRIx64, ctx->dest_iova);
> + rte_write64(SIZE_TO_CLS(ctx->dest_iova), ctx->addr + CSR_DST_ADDR);
> +
> + AFU_MF_PMD_DEBUG("dsm_addr: 0x%"PRIx64, ctx->dsm_iova);
> + rte_write32(SIZE_TO_CLS(ctx->dsm_iova), ctx->addr +
> CSR_AFU_DSM_BASEL);
> + rte_write32(SIZE_TO_CLS(ctx->dsm_iova) >> 32,
> + ctx->addr + CSR_AFU_DSM_BASEH);
> +
> + ret = he_lbk_afu_config(dev);
> + if (ret)
> + return ret;
> +
> + /* initialize src data */
> + ptr = (uint32_t *)ctx->src_ptr;
> + j = CLS_TO_SIZE(cfg->end) >> 2;
> + for (i = 0; i < j; i++)
> + *ptr++ = i;
> +
> + /* start test */
> + for (cl = cfg->begin; cl <= cfg->end; cl += cfg->multi_cl) {
> + memset(ctx->dest_ptr, 0, CLS_TO_SIZE(cl));
> + memset(ctx->dsm_ptr, 0, DSM_SIZE);
> +
> + ctl.csr = 0;
> + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> + rte_delay_us(1000);
> + ctl.reset = 1;
> + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> +
> + rte_write32(cl - 1, ctx->addr + CSR_NUM_LINES);
> +
> + ctl.start = 1;
> + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> +
> + if (cfg->cont) {
> + rte_delay_ms(cfg->timeout * 1000);
> + ctl.force_completion = 1;
> + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> + ret = dsm_poll_timeout(&ctx->status_ptr-
> >test_complete,
> + val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
> + DSM_TIMEOUT);
> + if (ret) {
> + printf("DSM poll timeout\n");
> + goto end;
> + }
> + } else {
> + ret = dsm_poll_timeout(&ctx->status_ptr-
> >test_complete,
> + val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
> + DSM_TIMEOUT);
> + if (ret) {
> + printf("DSM poll timeout\n");
> + goto end;
> + }
> + ctl.force_completion = 1;
> + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> + }
> +
> + he_lbk_report(dev, cl);
> +
> + i = 0;
> + while (i++ < 100) {
> + sval = rte_read64(ctx->addr + CSR_STATUS1);
> + if (sval == 0)
> + break;
> + rte_delay_us(1000);
> + }
> +
> + if (cfg->mode == NLB_MODE_LPBK) {
> + ptr = (uint32_t *)ctx->dest_ptr;
> + j = CLS_TO_SIZE(cl) >> 2;
> + for (i = 0; i < j; i++) {
> + if (*ptr++ != i) {
> + AFU_MF_PMD_ERR("Data mismatch @
> %u", i);
> + break;
> + }
> + }
> + }
> + }
> +
> +end:
> + return 0;
> +}
> +
> +static int he_lbk_ctx_release(struct afu_mf_rawdev *dev) {
> + struct he_lbk_priv *priv = NULL;
> + struct he_lbk_ctx *ctx = NULL;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + priv = (struct he_lbk_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + ctx = &priv->he_lbk_ctx;
> +
> + rte_free(ctx->dsm_ptr);
> + ctx->dsm_ptr = NULL;
> + ctx->status_ptr = NULL;
> +
> + rte_free(ctx->src_ptr);
> + ctx->src_ptr = NULL;
> +
> + rte_free(ctx->dest_ptr);
> + ctx->dest_ptr = NULL;
> +
> + return 0;
> +}
> +
> +static int he_lbk_ctx_init(struct afu_mf_rawdev *dev) {
> + struct he_lbk_priv *priv = NULL;
> + struct he_lbk_ctx *ctx = NULL;
> + int ret = 0;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + priv = (struct he_lbk_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + ctx = &priv->he_lbk_ctx;
> + ctx->addr = (uint8_t *)dev->addr;
> +
> + ctx->dsm_ptr = (uint8_t *)rte_zmalloc(NULL, DSM_SIZE,
> TEST_MEM_ALIGN);
> + if (!ctx->dsm_ptr) {
> + ret = -ENOMEM;
> + goto release;
> + }
> + ctx->dsm_iova = rte_malloc_virt2iova(ctx->dsm_ptr);
> + if (ctx->dsm_iova == RTE_BAD_IOVA) {
> + ret = -ENOMEM;
> + goto release;
> + }
> +
> + ctx->src_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
> + TEST_MEM_ALIGN);
> + if (!ctx->src_ptr) {
> + ret = -ENOMEM;
> + goto release;
If ctx->src_ptr alloc fail, he_lbk_ctx_release() can work?
> + }
> + ctx->src_iova = rte_malloc_virt2iova(ctx->src_ptr);
> + if (ctx->src_iova == RTE_BAD_IOVA) {
> + ret = -ENOMEM;
> + goto release;
> + }
> +
> + ctx->dest_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
> + TEST_MEM_ALIGN);
> + if (!ctx->dest_ptr) {
> + ret = -ENOMEM;
> + goto release;
> + }
> + ctx->dest_iova = rte_malloc_virt2iova(ctx->dest_ptr);
> + if (ctx->dest_iova == RTE_BAD_IOVA) {
> + ret = -ENOMEM;
> + goto release;
> + }
> +
> + ctx->status_ptr = (struct he_lbk_dsm_status *)ctx->dsm_ptr;
> + return 0;
> +
> +release:
> + he_lbk_ctx_release(dev);
> + return ret;
> +}
> +
> +static int he_lbk_init(struct afu_mf_rawdev *dev) {
> + if (!dev)
> + return -EINVAL;
> +
> + if (!dev->priv) {
> + dev->priv = rte_zmalloc(NULL, sizeof(struct he_lbk_priv), 0);
> + if (!dev->priv)
> + return -ENOMEM;
> + }
> +
> + return he_lbk_ctx_init(dev);
> +}
> +
> +static int he_lbk_config(struct afu_mf_rawdev *dev, void *config,
> + size_t config_size)
> +{
> + struct he_lbk_priv *priv = NULL;
> + struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
> +
> + if (!dev || !config || !config_size)
> + return -EINVAL;
> +
> + priv = (struct he_lbk_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + if (config_size != sizeof(struct rte_pmd_afu_he_lbk_cfg))
> + return -EINVAL;
> +
> + cfg = (struct rte_pmd_afu_he_lbk_cfg *)config;
> + if (cfg->mode > NLB_MODE_TRPUT)
> + return -EINVAL;
> + if ((cfg->multi_cl != 1) && (cfg->multi_cl != 2) &&
> + (cfg->multi_cl != 4))
> + return -EINVAL;
> + if ((cfg->begin < MIN_CACHE_LINES) || (cfg->begin >
> MAX_CACHE_LINES))
> + return -EINVAL;
> + if ((cfg->end < cfg->begin) || (cfg->end > MAX_CACHE_LINES))
> + return -EINVAL;
> +
> + rte_memcpy(&priv->he_lbk_cfg, cfg, sizeof(priv->he_lbk_cfg));
> +
> + return 0;
> +}
> +
> +static int he_lbk_close(struct afu_mf_rawdev *dev) {
> + if (!dev)
> + return -EINVAL;
> +
> + he_lbk_ctx_release(dev);
> +
> + rte_free(dev->priv);
> + dev->priv = NULL;
> +
> + return 0;
> +}
> +
> +static int he_lbk_dump(struct afu_mf_rawdev *dev, FILE *f) {
> + struct he_lbk_priv *priv = NULL;
> + struct he_lbk_ctx *ctx = NULL;
> +
> + if (!dev)
> + return -EINVAL;
> +
> + priv = (struct he_lbk_priv *)dev->priv;
> + if (!priv)
> + return -ENOENT;
> +
> + if (!f)
> + f = stdout;
> +
> + ctx = &priv->he_lbk_ctx;
> +
> + fprintf(f, "addr:\t\t%p\n", (void *)ctx->addr);
> + fprintf(f, "dsm_ptr:\t%p\n", (void *)ctx->dsm_ptr);
> + fprintf(f, "dsm_iova:\t0x%"PRIx64"\n", ctx->dsm_iova);
> + fprintf(f, "src_ptr:\t%p\n", (void *)ctx->src_ptr);
> + fprintf(f, "src_iova:\t0x%"PRIx64"\n", ctx->src_iova);
> + fprintf(f, "dest_ptr:\t%p\n", (void *)ctx->dest_ptr);
> + fprintf(f, "dest_iova:\t0x%"PRIx64"\n", ctx->dest_iova);
> + fprintf(f, "status_ptr:\t%p\n", (void *)ctx->status_ptr);
> +
> + return 0;
> +}
> +
> +static struct afu_mf_ops he_lbk_ops = {
> + .init = he_lbk_init,
> + .config = he_lbk_config,
> + .start = NULL,
> + .stop = NULL,
> + .test = he_lbk_test,
> + .close = he_lbk_close,
> + .dump = he_lbk_dump,
> + .reset = NULL
> +};
> +
> +struct afu_mf_drv he_lbk_drv = {
> + .uuid = { HE_LBK_UUID_L, HE_LBK_UUID_H },
> + .ops = &he_lbk_ops
> +};
> +
> +struct afu_mf_drv he_mem_lbk_drv = {
> + .uuid = { HE_MEM_LBK_UUID_L, HE_MEM_LBK_UUID_H },
> + .ops = &he_lbk_ops
> +};
> diff --git a/drivers/raw/afu_mf/he_lbk.h b/drivers/raw/afu_mf/he_lbk.h new file
> mode 100644 index 0000000..c2e8a29
> --- /dev/null
> +++ b/drivers/raw/afu_mf/he_lbk.h
> @@ -0,0 +1,121 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +#ifndef _HE_LBK_H_
> +#define _HE_LBK_H_
> +
> +#include "afu_mf_rawdev.h"
> +#include "rte_pmd_afu.h"
> +
> +#define HE_LBK_UUID_L 0xb94b12284c31e02b
> +#define HE_LBK_UUID_H 0x56e203e9864f49a7
> +#define HE_MEM_LBK_UUID_L 0xbb652a578330a8eb #define
> HE_MEM_LBK_UUID_H
> +0x8568ab4e6ba54616
> +
> +extern struct afu_mf_drv he_lbk_drv;
> +extern struct afu_mf_drv he_mem_lbk_drv;
> +
> +/* HE-LBK & HE-MEM-LBK registers definition */
> +#define CSR_SCRATCHPAD0 0x100
> +#define CSR_SCRATCHPAD1 0x108
> +#define CSR_AFU_DSM_BASEL 0x110
> +#define CSR_AFU_DSM_BASEH 0x114
> +#define CSR_SRC_ADDR 0x120
> +#define CSR_DST_ADDR 0x128
> +#define CSR_NUM_LINES 0x130
> +#define CSR_CTL 0x138
> +#define CSR_CFG 0x140
> +#define CSR_INACT_THRESH 0x148
> +#define CSR_INTERRUPT0 0x150
> +#define CSR_SWTEST_MSG 0x158
> +#define CSR_STATUS0 0x160
> +#define CSR_STATUS1 0x168
> +#define CSR_ERROR 0x170
> +#define CSR_STRIDE 0x178
> +#define CSR_HE_INFO0 0x180
> +
> +#define DSM_SIZE 0x200000
> +#define DSM_POLL_INTERVAL 5 /* ms */
> +#define DSM_TIMEOUT 1000 /* ms */
> +
> +#define NLB_BUF_SIZE 0x400000
> +#define TEST_MEM_ALIGN 1024
> +
> +struct he_lbk_csr_ctl {
> + union {
> + uint32_t csr;
> + struct {
> + uint32_t reset:1;
> + uint32_t start:1;
> + uint32_t force_completion:1;
> + uint32_t reserved:29;
> + };
> + };
> +};
> +
> +struct he_lbk_csr_cfg {
> + union {
> + uint32_t csr;
> + struct {
> + uint32_t rsvd1:1;
> + uint32_t cont:1;
> + uint32_t mode:3;
> + uint32_t multicl_len:2;
> + uint32_t rsvd2:13;
> + uint32_t trput_interleave:3;
> + uint32_t test_cfg:5;
> + uint32_t interrupt_on_error:1;
> + uint32_t interrupt_testmode:1;
> + uint32_t rsvd3:2;
> + };
> + };
> +};
> +
> +struct he_lbk_status0 {
> + union {
> + uint64_t csr;
> + struct {
> + uint32_t num_writes;
> + uint32_t num_reads;
> + };
> + };
> +};
> +
> +struct he_lbk_status1 {
> + union {
> + uint64_t csr;
> + struct {
> + uint32_t num_pend_writes;
> + uint32_t num_pend_reads;
> + };
> + };
> +};
> +
> +struct he_lbk_dsm_status {
> + uint32_t test_complete;
> + uint32_t test_error;
> + uint64_t num_clocks;
> + uint32_t num_reads;
> + uint32_t num_writes;
> + uint32_t start_overhead;
> + uint32_t end_overhead;
> +};
> +
> +struct he_lbk_ctx {
> + uint8_t *addr;
> + uint8_t *dsm_ptr;
> + uint64_t dsm_iova;
> + uint8_t *src_ptr;
> + uint64_t src_iova;
> + uint8_t *dest_ptr;
> + uint64_t dest_iova;
> + struct he_lbk_dsm_status *status_ptr;
> +};
> +
> +struct he_lbk_priv {
> + struct rte_pmd_afu_he_lbk_cfg he_lbk_cfg;
> + struct he_lbk_ctx he_lbk_ctx;
> +};
> +
> +#endif /* _HE_LBK_H_ */
> diff --git a/drivers/raw/afu_mf/meson.build b/drivers/raw/afu_mf/meson.build
> index 8a989e3..a983f53 100644
> --- a/drivers/raw/afu_mf/meson.build
> +++ b/drivers/raw/afu_mf/meson.build
> @@ -2,6 +2,6 @@
> # Copyright 2022 Intel Corporation
>
> deps += ['rawdev', 'bus_pci', 'bus_ifpga'] -sources = files('afu_mf_rawdev.c',
> 'n3000_afu.c')
> +sources = files('afu_mf_rawdev.c', 'n3000_afu.c', 'he_lbk.c')
>
> headers = files('rte_pmd_afu.h')
> diff --git a/drivers/raw/afu_mf/rte_pmd_afu.h
> b/drivers/raw/afu_mf/rte_pmd_afu.h
> index f14a053..658df55 100644
> --- a/drivers/raw/afu_mf/rte_pmd_afu.h
> +++ b/drivers/raw/afu_mf/rte_pmd_afu.h
> @@ -90,6 +90,20 @@ struct rte_pmd_afu_n3000_cfg {
> };
> };
>
> +/**
> + * HE-LBK & HE-MEM-LBK AFU configuration data structure.
> + */
> +struct rte_pmd_afu_he_lbk_cfg {
> + uint32_t mode;
> + uint32_t begin;
> + uint32_t end;
> + uint32_t multi_cl;
> + uint32_t cont;
> + uint32_t timeout;
> + uint32_t trput_interleave;
> + uint32_t freq_mhz;
> +};
> +
> #ifdef __cplusplus
> }
> #endif
> --
> 1.8.3.1
> -----Original Message-----
> From: Zhang, Tianfei <tianfei.zhang@intel.com>
> Sent: Monday, June 6, 2022 09:41
> To: Huang, Wei <wei.huang@intel.com>; dev@dpdk.org;
> thomas@monjalon.net; nipun.gupta@nxp.com; hemant.agrawal@nxp.com
> Cc: stable@dpdk.org; Xu, Rosen <rosen.xu@intel.com>; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: RE: [PATCH v5 3/5] raw/afu_mf: add HE-LBK AFU driver
>
>
>
> > -----Original Message-----
> > From: Huang, Wei <wei.huang@intel.com>
> > Sent: Friday, May 27, 2022 1:37 PM
> > To: dev@dpdk.org; thomas@monjalon.net; nipun.gupta@nxp.com;
> > hemant.agrawal@nxp.com
> > Cc: stable@dpdk.org; Xu, Rosen <rosen.xu@intel.com>; Zhang, Tianfei
> > <tianfei.zhang@intel.com>; Zhang, Qi Z <qi.z.zhang@intel.com>; Huang,
> > Wei <wei.huang@intel.com>
> > Subject: [PATCH v5 3/5] raw/afu_mf: add HE-LBK AFU driver
> >
> > HE-LBK and HE-MEM-LBK are host exerciser modules in OFS FPGA, HE-LBK
> > is used to test PCI bus and HE-MEM-LBK is used to test local memory.
> > This driver initialize the modules and report test result.
> >
> > Signed-off-by: Wei Huang <wei.huang@intel.com>
> > ---
> > drivers/raw/afu_mf/afu_mf_rawdev.c | 5 +
> > drivers/raw/afu_mf/he_lbk.c | 427
> > +++++++++++++++++++++++++++++++++++++
> > drivers/raw/afu_mf/he_lbk.h | 121 +++++++++++
> > drivers/raw/afu_mf/meson.build | 2 +-
> > drivers/raw/afu_mf/rte_pmd_afu.h | 14 ++
> > 5 files changed, 568 insertions(+), 1 deletion(-) create mode 100644
> > drivers/raw/afu_mf/he_lbk.c create mode 100644
> > drivers/raw/afu_mf/he_lbk.h
> >
> > diff --git a/drivers/raw/afu_mf/afu_mf_rawdev.c
> > b/drivers/raw/afu_mf/afu_mf_rawdev.c
> > index 7c18f3b..e91eb21 100644
> > --- a/drivers/raw/afu_mf/afu_mf_rawdev.c
> > +++ b/drivers/raw/afu_mf/afu_mf_rawdev.c
> > @@ -20,16 +20,21 @@
> > #include "rte_pmd_afu.h"
> > #include "afu_mf_rawdev.h"
> > #include "n3000_afu.h"
> > +#include "he_lbk.h"
> >
> > #define AFU_MF_PMD_RAWDEV_NAME rawdev_afu_mf
> >
> > static const struct rte_afu_uuid afu_uuid_map[] = {
> > { N3000_AFU_UUID_L, N3000_AFU_UUID_H },
> > + { HE_LBK_UUID_L, HE_LBK_UUID_H },
> > + { HE_MEM_LBK_UUID_L, HE_MEM_LBK_UUID_H },
> > { 0, 0 /* sentinel */ }
> > };
> >
> > static struct afu_mf_drv *afu_table[] = {
> > &n3000_afu_drv,
> > + &he_lbk_drv,
> > + &he_mem_lbk_drv,
> > NULL
> > };
> >
> > diff --git a/drivers/raw/afu_mf/he_lbk.c b/drivers/raw/afu_mf/he_lbk.c
> > new file mode 100644 index 0000000..8735647
> > --- /dev/null
> > +++ b/drivers/raw/afu_mf/he_lbk.c
> > @@ -0,0 +1,427 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2022 Intel Corporation */
> > +
> > +#include <errno.h>
> > +#include <stdio.h>
> > +#include <stdint.h>
> > +#include <stdlib.h>
> > +#include <inttypes.h>
> > +#include <unistd.h>
> > +#include <fcntl.h>
> > +#include <poll.h>
> > +#include <sys/eventfd.h>
> > +#include <sys/ioctl.h>
> > +
> > +#include <rte_eal.h>
> > +#include <rte_malloc.h>
> > +#include <rte_memcpy.h>
> > +#include <rte_io.h>
> > +#include <rte_vfio.h>
> > +#include <rte_bus_pci.h>
> > +#include <rte_bus_ifpga.h>
> > +#include <rte_rawdev.h>
> > +
> > +#include "afu_mf_rawdev.h"
> > +#include "he_lbk.h"
> > +
> > +static int he_lbk_afu_config(struct afu_mf_rawdev *dev) {
> > + struct he_lbk_priv *priv = NULL;
> > + struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
> > + struct he_lbk_csr_cfg v;
> > +
> > + if (!dev)
> > + return -EINVAL;
> > +
> > + priv = (struct he_lbk_priv *)dev->priv;
> > + if (!priv)
> > + return -ENOENT;
> > +
> > + cfg = &priv->he_lbk_cfg;
> > +
> > + v.csr = 0;
> > +
> > + if (cfg->cont)
> > + v.cont = 1;
> > +
> > + v.mode = cfg->mode;
> > + v.trput_interleave = cfg->trput_interleave;
> > + if (cfg->multi_cl == 4)
> > + v.multicl_len = 2;
> > + else
> > + v.multicl_len = cfg->multi_cl - 1;
> > +
> > + AFU_MF_PMD_DEBUG("cfg: 0x%08x", v.csr);
> > + rte_write32(v.csr, priv->he_lbk_ctx.addr + CSR_CFG);
> > +
> > + return 0;
> > +}
> > +
> > +static void he_lbk_report(struct afu_mf_rawdev *dev, uint32_t cl) {
> > + struct he_lbk_priv *priv = NULL;
> > + struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
> > + struct he_lbk_ctx *ctx = NULL;
> > + struct he_lbk_dsm_status *stat = NULL;
> > + struct he_lbk_status0 stat0;
> > + struct he_lbk_status1 stat1;
> > + uint64_t swtest_msg = 0;
> > + uint64_t ticks = 0;
> > + uint64_t info = 0;
> > + double num, rd_bw, wr_bw;
> > +
> > + if (!dev || !dev->priv)
> > + return;
> > +
> > + priv = (struct he_lbk_priv *)dev->priv;
> > + cfg = &priv->he_lbk_cfg;
> > + ctx = &priv->he_lbk_ctx;
> > +
> > + stat = ctx->status_ptr;
> > +
> > + swtest_msg = rte_read64(ctx->addr + CSR_SWTEST_MSG);
> > + stat0.csr = rte_read64(ctx->addr + CSR_STATUS0);
> > + stat1.csr = rte_read64(ctx->addr + CSR_STATUS1);
> > +
> > + if (cfg->cont)
> > + ticks = stat->num_clocks - stat->start_overhead;
> > + else
> > + ticks = stat->num_clocks -
> > + (stat->start_overhead + stat->end_overhead);
> > +
> > + if (cfg->freq_mhz == 0) {
> > + info = rte_read64(ctx->addr + CSR_HE_INFO0);
> > + AFU_MF_PMD_INFO("API version: %"PRIx64, info >> 16);
> > + cfg->freq_mhz = info & 0xffff;
> > + if (cfg->freq_mhz == 0) {
> > + AFU_MF_PMD_INFO("Frequency of AFU clock is
> > unknown."
> > + " Assuming 350 MHz.");
> > + cfg->freq_mhz = 350;
> > + }
> > + }
> > +
> > + num = (double)stat0.num_reads;
> > + rd_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
> > + num = (double)stat0.num_writes;
> > + wr_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
> > +
> > + printf("Cachelines Read_Count Write_Count Pend_Read
> Pend_Write "
> > + "Clocks@%uMHz Rd_Bandwidth Wr_Bandwidth\n",
> > + cfg->freq_mhz);
> > + printf("%10u %10u %10u %10u %10u %12"PRIu64
> > + " %7.3f GB/s %7.3f GB/s\n",
> > + cl, stat0.num_reads, stat0.num_writes,
> > + stat1.num_pend_reads, stat1.num_pend_writes,
> > + ticks, rd_bw / 1e9, wr_bw / 1e9);
> > + printf("Test Message: 0x%"PRIx64"\n", swtest_msg); }
> > +
> > +static int he_lbk_test(struct afu_mf_rawdev *dev) {
> > + struct he_lbk_priv *priv = NULL;
> > + struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
> > + struct he_lbk_ctx *ctx = NULL;
> > + struct he_lbk_csr_ctl ctl;
> > + uint32_t *ptr = NULL;
> > + uint32_t i, j, cl, val = 0;
> > + uint64_t sval = 0;
> > + int ret = 0;
> > +
> > + if (!dev)
> > + return -EINVAL;
> > +
> > + priv = (struct he_lbk_priv *)dev->priv;
> > + if (!priv)
> > + return -ENOENT;
> > +
> > + cfg = &priv->he_lbk_cfg;
> > + ctx = &priv->he_lbk_ctx;
> > +
> > + ctl.csr = 0;
> > + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> > + rte_delay_us(1000);
> > + ctl.reset = 1;
> > + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> > +
> > + /* initialize DMA addresses */
> > + AFU_MF_PMD_DEBUG("src_addr: 0x%"PRIx64, ctx->src_iova);
> > + rte_write64(SIZE_TO_CLS(ctx->src_iova), ctx->addr +
> CSR_SRC_ADDR);
> > +
> > + AFU_MF_PMD_DEBUG("dst_addr: 0x%"PRIx64, ctx->dest_iova);
> > + rte_write64(SIZE_TO_CLS(ctx->dest_iova), ctx->addr +
> CSR_DST_ADDR);
> > +
> > + AFU_MF_PMD_DEBUG("dsm_addr: 0x%"PRIx64, ctx->dsm_iova);
> > + rte_write32(SIZE_TO_CLS(ctx->dsm_iova), ctx->addr +
> > CSR_AFU_DSM_BASEL);
> > + rte_write32(SIZE_TO_CLS(ctx->dsm_iova) >> 32,
> > + ctx->addr + CSR_AFU_DSM_BASEH);
> > +
> > + ret = he_lbk_afu_config(dev);
> > + if (ret)
> > + return ret;
> > +
> > + /* initialize src data */
> > + ptr = (uint32_t *)ctx->src_ptr;
> > + j = CLS_TO_SIZE(cfg->end) >> 2;
> > + for (i = 0; i < j; i++)
> > + *ptr++ = i;
> > +
> > + /* start test */
> > + for (cl = cfg->begin; cl <= cfg->end; cl += cfg->multi_cl) {
> > + memset(ctx->dest_ptr, 0, CLS_TO_SIZE(cl));
> > + memset(ctx->dsm_ptr, 0, DSM_SIZE);
> > +
> > + ctl.csr = 0;
> > + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> > + rte_delay_us(1000);
> > + ctl.reset = 1;
> > + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> > +
> > + rte_write32(cl - 1, ctx->addr + CSR_NUM_LINES);
> > +
> > + ctl.start = 1;
> > + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> > +
> > + if (cfg->cont) {
> > + rte_delay_ms(cfg->timeout * 1000);
> > + ctl.force_completion = 1;
> > + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> > + ret = dsm_poll_timeout(&ctx->status_ptr-
> > >test_complete,
> > + val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
> > + DSM_TIMEOUT);
> > + if (ret) {
> > + printf("DSM poll timeout\n");
> > + goto end;
> > + }
> > + } else {
> > + ret = dsm_poll_timeout(&ctx->status_ptr-
> > >test_complete,
> > + val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
> > + DSM_TIMEOUT);
> > + if (ret) {
> > + printf("DSM poll timeout\n");
> > + goto end;
> > + }
> > + ctl.force_completion = 1;
> > + rte_write32(ctl.csr, ctx->addr + CSR_CTL);
> > + }
> > +
> > + he_lbk_report(dev, cl);
> > +
> > + i = 0;
> > + while (i++ < 100) {
> > + sval = rte_read64(ctx->addr + CSR_STATUS1);
> > + if (sval == 0)
> > + break;
> > + rte_delay_us(1000);
> > + }
> > +
> > + if (cfg->mode == NLB_MODE_LPBK) {
> > + ptr = (uint32_t *)ctx->dest_ptr;
> > + j = CLS_TO_SIZE(cl) >> 2;
> > + for (i = 0; i < j; i++) {
> > + if (*ptr++ != i) {
> > + AFU_MF_PMD_ERR("Data mismatch
> @
> > %u", i);
> > + break;
> > + }
> > + }
> > + }
> > + }
> > +
> > +end:
> > + return 0;
> > +}
> > +
> > +static int he_lbk_ctx_release(struct afu_mf_rawdev *dev) {
> > + struct he_lbk_priv *priv = NULL;
> > + struct he_lbk_ctx *ctx = NULL;
> > +
> > + if (!dev)
> > + return -EINVAL;
> > +
> > + priv = (struct he_lbk_priv *)dev->priv;
> > + if (!priv)
> > + return -ENOENT;
> > +
> > + ctx = &priv->he_lbk_ctx;
> > +
> > + rte_free(ctx->dsm_ptr);
> > + ctx->dsm_ptr = NULL;
> > + ctx->status_ptr = NULL;
> > +
> > + rte_free(ctx->src_ptr);
> > + ctx->src_ptr = NULL;
> > +
> > + rte_free(ctx->dest_ptr);
> > + ctx->dest_ptr = NULL;
> > +
> > + return 0;
> > +}
> > +
> > +static int he_lbk_ctx_init(struct afu_mf_rawdev *dev) {
> > + struct he_lbk_priv *priv = NULL;
> > + struct he_lbk_ctx *ctx = NULL;
> > + int ret = 0;
> > +
> > + if (!dev)
> > + return -EINVAL;
> > +
> > + priv = (struct he_lbk_priv *)dev->priv;
> > + if (!priv)
> > + return -ENOENT;
> > +
> > + ctx = &priv->he_lbk_ctx;
> > + ctx->addr = (uint8_t *)dev->addr;
> > +
> > + ctx->dsm_ptr = (uint8_t *)rte_zmalloc(NULL, DSM_SIZE,
> > TEST_MEM_ALIGN);
> > + if (!ctx->dsm_ptr) {
> > + ret = -ENOMEM;
> > + goto release;
> > + }
> > + ctx->dsm_iova = rte_malloc_virt2iova(ctx->dsm_ptr);
> > + if (ctx->dsm_iova == RTE_BAD_IOVA) {
> > + ret = -ENOMEM;
> > + goto release;
> > + }
> > +
> > + ctx->src_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
> > + TEST_MEM_ALIGN);
> > + if (!ctx->src_ptr) {
> > + ret = -ENOMEM;
> > + goto release;
>
> If ctx->src_ptr alloc fail, he_lbk_ctx_release() can work?
>
He_lbk_ctx_release() can work correct in failure situation, but it's not standard exception handle, I will change it.
> > + }
> > + ctx->src_iova = rte_malloc_virt2iova(ctx->src_ptr);
> > + if (ctx->src_iova == RTE_BAD_IOVA) {
> > + ret = -ENOMEM;
> > + goto release;
> > + }
> > +
> > + ctx->dest_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
> > + TEST_MEM_ALIGN);
> > + if (!ctx->dest_ptr) {
> > + ret = -ENOMEM;
> > + goto release;
> > + }
> > + ctx->dest_iova = rte_malloc_virt2iova(ctx->dest_ptr);
> > + if (ctx->dest_iova == RTE_BAD_IOVA) {
> > + ret = -ENOMEM;
> > + goto release;
> > + }
> > +
> > + ctx->status_ptr = (struct he_lbk_dsm_status *)ctx->dsm_ptr;
> > + return 0;
> > +
> > +release:
> > + he_lbk_ctx_release(dev);
> > + return ret;
> > +}
> > +
> > +static int he_lbk_init(struct afu_mf_rawdev *dev) {
> > + if (!dev)
> > + return -EINVAL;
> > +
> > + if (!dev->priv) {
> > + dev->priv = rte_zmalloc(NULL, sizeof(struct he_lbk_priv), 0);
> > + if (!dev->priv)
> > + return -ENOMEM;
> > + }
> > +
> > + return he_lbk_ctx_init(dev);
> > +}
> > +
> > +static int he_lbk_config(struct afu_mf_rawdev *dev, void *config,
> > + size_t config_size)
> > +{
> > + struct he_lbk_priv *priv = NULL;
> > + struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
> > +
> > + if (!dev || !config || !config_size)
> > + return -EINVAL;
> > +
> > + priv = (struct he_lbk_priv *)dev->priv;
> > + if (!priv)
> > + return -ENOENT;
> > +
> > + if (config_size != sizeof(struct rte_pmd_afu_he_lbk_cfg))
> > + return -EINVAL;
> > +
> > + cfg = (struct rte_pmd_afu_he_lbk_cfg *)config;
> > + if (cfg->mode > NLB_MODE_TRPUT)
> > + return -EINVAL;
> > + if ((cfg->multi_cl != 1) && (cfg->multi_cl != 2) &&
> > + (cfg->multi_cl != 4))
> > + return -EINVAL;
> > + if ((cfg->begin < MIN_CACHE_LINES) || (cfg->begin >
> > MAX_CACHE_LINES))
> > + return -EINVAL;
> > + if ((cfg->end < cfg->begin) || (cfg->end > MAX_CACHE_LINES))
> > + return -EINVAL;
> > +
> > + rte_memcpy(&priv->he_lbk_cfg, cfg, sizeof(priv->he_lbk_cfg));
> > +
> > + return 0;
> > +}
> > +
> > +static int he_lbk_close(struct afu_mf_rawdev *dev) {
> > + if (!dev)
> > + return -EINVAL;
> > +
> > + he_lbk_ctx_release(dev);
> > +
> > + rte_free(dev->priv);
> > + dev->priv = NULL;
> > +
> > + return 0;
> > +}
> > +
> > +static int he_lbk_dump(struct afu_mf_rawdev *dev, FILE *f) {
> > + struct he_lbk_priv *priv = NULL;
> > + struct he_lbk_ctx *ctx = NULL;
> > +
> > + if (!dev)
> > + return -EINVAL;
> > +
> > + priv = (struct he_lbk_priv *)dev->priv;
> > + if (!priv)
> > + return -ENOENT;
> > +
> > + if (!f)
> > + f = stdout;
> > +
> > + ctx = &priv->he_lbk_ctx;
> > +
> > + fprintf(f, "addr:\t\t%p\n", (void *)ctx->addr);
> > + fprintf(f, "dsm_ptr:\t%p\n", (void *)ctx->dsm_ptr);
> > + fprintf(f, "dsm_iova:\t0x%"PRIx64"\n", ctx->dsm_iova);
> > + fprintf(f, "src_ptr:\t%p\n", (void *)ctx->src_ptr);
> > + fprintf(f, "src_iova:\t0x%"PRIx64"\n", ctx->src_iova);
> > + fprintf(f, "dest_ptr:\t%p\n", (void *)ctx->dest_ptr);
> > + fprintf(f, "dest_iova:\t0x%"PRIx64"\n", ctx->dest_iova);
> > + fprintf(f, "status_ptr:\t%p\n", (void *)ctx->status_ptr);
> > +
> > + return 0;
> > +}
> > +
> > +static struct afu_mf_ops he_lbk_ops = {
> > + .init = he_lbk_init,
> > + .config = he_lbk_config,
> > + .start = NULL,
> > + .stop = NULL,
> > + .test = he_lbk_test,
> > + .close = he_lbk_close,
> > + .dump = he_lbk_dump,
> > + .reset = NULL
> > +};
> > +
> > +struct afu_mf_drv he_lbk_drv = {
> > + .uuid = { HE_LBK_UUID_L, HE_LBK_UUID_H },
> > + .ops = &he_lbk_ops
> > +};
> > +
> > +struct afu_mf_drv he_mem_lbk_drv = {
> > + .uuid = { HE_MEM_LBK_UUID_L, HE_MEM_LBK_UUID_H },
> > + .ops = &he_lbk_ops
> > +};
> > diff --git a/drivers/raw/afu_mf/he_lbk.h b/drivers/raw/afu_mf/he_lbk.h
> > new file mode 100644 index 0000000..c2e8a29
> > --- /dev/null
> > +++ b/drivers/raw/afu_mf/he_lbk.h
> > @@ -0,0 +1,121 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2022 Intel Corporation */
> > +
> > +#ifndef _HE_LBK_H_
> > +#define _HE_LBK_H_
> > +
> > +#include "afu_mf_rawdev.h"
> > +#include "rte_pmd_afu.h"
> > +
> > +#define HE_LBK_UUID_L 0xb94b12284c31e02b
> > +#define HE_LBK_UUID_H 0x56e203e9864f49a7
> > +#define HE_MEM_LBK_UUID_L 0xbb652a578330a8eb #define
> > HE_MEM_LBK_UUID_H
> > +0x8568ab4e6ba54616
> > +
> > +extern struct afu_mf_drv he_lbk_drv;
> > +extern struct afu_mf_drv he_mem_lbk_drv;
> > +
> > +/* HE-LBK & HE-MEM-LBK registers definition */
> > +#define CSR_SCRATCHPAD0 0x100
> > +#define CSR_SCRATCHPAD1 0x108
> > +#define CSR_AFU_DSM_BASEL 0x110
> > +#define CSR_AFU_DSM_BASEH 0x114
> > +#define CSR_SRC_ADDR 0x120
> > +#define CSR_DST_ADDR 0x128
> > +#define CSR_NUM_LINES 0x130
> > +#define CSR_CTL 0x138
> > +#define CSR_CFG 0x140
> > +#define CSR_INACT_THRESH 0x148
> > +#define CSR_INTERRUPT0 0x150
> > +#define CSR_SWTEST_MSG 0x158
> > +#define CSR_STATUS0 0x160
> > +#define CSR_STATUS1 0x168
> > +#define CSR_ERROR 0x170
> > +#define CSR_STRIDE 0x178
> > +#define CSR_HE_INFO0 0x180
> > +
> > +#define DSM_SIZE 0x200000
> > +#define DSM_POLL_INTERVAL 5 /* ms */
> > +#define DSM_TIMEOUT 1000 /* ms */
> > +
> > +#define NLB_BUF_SIZE 0x400000
> > +#define TEST_MEM_ALIGN 1024
> > +
> > +struct he_lbk_csr_ctl {
> > + union {
> > + uint32_t csr;
> > + struct {
> > + uint32_t reset:1;
> > + uint32_t start:1;
> > + uint32_t force_completion:1;
> > + uint32_t reserved:29;
> > + };
> > + };
> > +};
> > +
> > +struct he_lbk_csr_cfg {
> > + union {
> > + uint32_t csr;
> > + struct {
> > + uint32_t rsvd1:1;
> > + uint32_t cont:1;
> > + uint32_t mode:3;
> > + uint32_t multicl_len:2;
> > + uint32_t rsvd2:13;
> > + uint32_t trput_interleave:3;
> > + uint32_t test_cfg:5;
> > + uint32_t interrupt_on_error:1;
> > + uint32_t interrupt_testmode:1;
> > + uint32_t rsvd3:2;
> > + };
> > + };
> > +};
> > +
> > +struct he_lbk_status0 {
> > + union {
> > + uint64_t csr;
> > + struct {
> > + uint32_t num_writes;
> > + uint32_t num_reads;
> > + };
> > + };
> > +};
> > +
> > +struct he_lbk_status1 {
> > + union {
> > + uint64_t csr;
> > + struct {
> > + uint32_t num_pend_writes;
> > + uint32_t num_pend_reads;
> > + };
> > + };
> > +};
> > +
> > +struct he_lbk_dsm_status {
> > + uint32_t test_complete;
> > + uint32_t test_error;
> > + uint64_t num_clocks;
> > + uint32_t num_reads;
> > + uint32_t num_writes;
> > + uint32_t start_overhead;
> > + uint32_t end_overhead;
> > +};
> > +
> > +struct he_lbk_ctx {
> > + uint8_t *addr;
> > + uint8_t *dsm_ptr;
> > + uint64_t dsm_iova;
> > + uint8_t *src_ptr;
> > + uint64_t src_iova;
> > + uint8_t *dest_ptr;
> > + uint64_t dest_iova;
> > + struct he_lbk_dsm_status *status_ptr; };
> > +
> > +struct he_lbk_priv {
> > + struct rte_pmd_afu_he_lbk_cfg he_lbk_cfg;
> > + struct he_lbk_ctx he_lbk_ctx;
> > +};
> > +
> > +#endif /* _HE_LBK_H_ */
> > diff --git a/drivers/raw/afu_mf/meson.build
> > b/drivers/raw/afu_mf/meson.build index 8a989e3..a983f53 100644
> > --- a/drivers/raw/afu_mf/meson.build
> > +++ b/drivers/raw/afu_mf/meson.build
> > @@ -2,6 +2,6 @@
> > # Copyright 2022 Intel Corporation
> >
> > deps += ['rawdev', 'bus_pci', 'bus_ifpga'] -sources =
> > files('afu_mf_rawdev.c',
> > 'n3000_afu.c')
> > +sources = files('afu_mf_rawdev.c', 'n3000_afu.c', 'he_lbk.c')
> >
> > headers = files('rte_pmd_afu.h')
> > diff --git a/drivers/raw/afu_mf/rte_pmd_afu.h
> > b/drivers/raw/afu_mf/rte_pmd_afu.h
> > index f14a053..658df55 100644
> > --- a/drivers/raw/afu_mf/rte_pmd_afu.h
> > +++ b/drivers/raw/afu_mf/rte_pmd_afu.h
> > @@ -90,6 +90,20 @@ struct rte_pmd_afu_n3000_cfg {
> > };
> > };
> >
> > +/**
> > + * HE-LBK & HE-MEM-LBK AFU configuration data structure.
> > + */
> > +struct rte_pmd_afu_he_lbk_cfg {
> > + uint32_t mode;
> > + uint32_t begin;
> > + uint32_t end;
> > + uint32_t multi_cl;
> > + uint32_t cont;
> > + uint32_t timeout;
> > + uint32_t trput_interleave;
> > + uint32_t freq_mhz;
> > +};
> > +
> > #ifdef __cplusplus
> > }
> > #endif
> > --
> > 1.8.3.1
@@ -20,16 +20,21 @@
#include "rte_pmd_afu.h"
#include "afu_mf_rawdev.h"
#include "n3000_afu.h"
+#include "he_lbk.h"
#define AFU_MF_PMD_RAWDEV_NAME rawdev_afu_mf
static const struct rte_afu_uuid afu_uuid_map[] = {
{ N3000_AFU_UUID_L, N3000_AFU_UUID_H },
+ { HE_LBK_UUID_L, HE_LBK_UUID_H },
+ { HE_MEM_LBK_UUID_L, HE_MEM_LBK_UUID_H },
{ 0, 0 /* sentinel */ }
};
static struct afu_mf_drv *afu_table[] = {
&n3000_afu_drv,
+ &he_lbk_drv,
+ &he_mem_lbk_drv,
NULL
};
new file mode 100644
@@ -0,0 +1,427 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Intel Corporation
+ */
+
+#include <errno.h>
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <inttypes.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <poll.h>
+#include <sys/eventfd.h>
+#include <sys/ioctl.h>
+
+#include <rte_eal.h>
+#include <rte_malloc.h>
+#include <rte_memcpy.h>
+#include <rte_io.h>
+#include <rte_vfio.h>
+#include <rte_bus_pci.h>
+#include <rte_bus_ifpga.h>
+#include <rte_rawdev.h>
+
+#include "afu_mf_rawdev.h"
+#include "he_lbk.h"
+
+static int he_lbk_afu_config(struct afu_mf_rawdev *dev)
+{
+ struct he_lbk_priv *priv = NULL;
+ struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
+ struct he_lbk_csr_cfg v;
+
+ if (!dev)
+ return -EINVAL;
+
+ priv = (struct he_lbk_priv *)dev->priv;
+ if (!priv)
+ return -ENOENT;
+
+ cfg = &priv->he_lbk_cfg;
+
+ v.csr = 0;
+
+ if (cfg->cont)
+ v.cont = 1;
+
+ v.mode = cfg->mode;
+ v.trput_interleave = cfg->trput_interleave;
+ if (cfg->multi_cl == 4)
+ v.multicl_len = 2;
+ else
+ v.multicl_len = cfg->multi_cl - 1;
+
+ AFU_MF_PMD_DEBUG("cfg: 0x%08x", v.csr);
+ rte_write32(v.csr, priv->he_lbk_ctx.addr + CSR_CFG);
+
+ return 0;
+}
+
+static void he_lbk_report(struct afu_mf_rawdev *dev, uint32_t cl)
+{
+ struct he_lbk_priv *priv = NULL;
+ struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
+ struct he_lbk_ctx *ctx = NULL;
+ struct he_lbk_dsm_status *stat = NULL;
+ struct he_lbk_status0 stat0;
+ struct he_lbk_status1 stat1;
+ uint64_t swtest_msg = 0;
+ uint64_t ticks = 0;
+ uint64_t info = 0;
+ double num, rd_bw, wr_bw;
+
+ if (!dev || !dev->priv)
+ return;
+
+ priv = (struct he_lbk_priv *)dev->priv;
+ cfg = &priv->he_lbk_cfg;
+ ctx = &priv->he_lbk_ctx;
+
+ stat = ctx->status_ptr;
+
+ swtest_msg = rte_read64(ctx->addr + CSR_SWTEST_MSG);
+ stat0.csr = rte_read64(ctx->addr + CSR_STATUS0);
+ stat1.csr = rte_read64(ctx->addr + CSR_STATUS1);
+
+ if (cfg->cont)
+ ticks = stat->num_clocks - stat->start_overhead;
+ else
+ ticks = stat->num_clocks -
+ (stat->start_overhead + stat->end_overhead);
+
+ if (cfg->freq_mhz == 0) {
+ info = rte_read64(ctx->addr + CSR_HE_INFO0);
+ AFU_MF_PMD_INFO("API version: %"PRIx64, info >> 16);
+ cfg->freq_mhz = info & 0xffff;
+ if (cfg->freq_mhz == 0) {
+ AFU_MF_PMD_INFO("Frequency of AFU clock is unknown."
+ " Assuming 350 MHz.");
+ cfg->freq_mhz = 350;
+ }
+ }
+
+ num = (double)stat0.num_reads;
+ rd_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
+ num = (double)stat0.num_writes;
+ wr_bw = (num * CLS_TO_SIZE(1) * MHZ(cfg->freq_mhz)) / ticks;
+
+ printf("Cachelines Read_Count Write_Count Pend_Read Pend_Write "
+ "Clocks@%uMHz Rd_Bandwidth Wr_Bandwidth\n",
+ cfg->freq_mhz);
+ printf("%10u %10u %10u %10u %10u %12"PRIu64
+ " %7.3f GB/s %7.3f GB/s\n",
+ cl, stat0.num_reads, stat0.num_writes,
+ stat1.num_pend_reads, stat1.num_pend_writes,
+ ticks, rd_bw / 1e9, wr_bw / 1e9);
+ printf("Test Message: 0x%"PRIx64"\n", swtest_msg);
+}
+
+static int he_lbk_test(struct afu_mf_rawdev *dev)
+{
+ struct he_lbk_priv *priv = NULL;
+ struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
+ struct he_lbk_ctx *ctx = NULL;
+ struct he_lbk_csr_ctl ctl;
+ uint32_t *ptr = NULL;
+ uint32_t i, j, cl, val = 0;
+ uint64_t sval = 0;
+ int ret = 0;
+
+ if (!dev)
+ return -EINVAL;
+
+ priv = (struct he_lbk_priv *)dev->priv;
+ if (!priv)
+ return -ENOENT;
+
+ cfg = &priv->he_lbk_cfg;
+ ctx = &priv->he_lbk_ctx;
+
+ ctl.csr = 0;
+ rte_write32(ctl.csr, ctx->addr + CSR_CTL);
+ rte_delay_us(1000);
+ ctl.reset = 1;
+ rte_write32(ctl.csr, ctx->addr + CSR_CTL);
+
+ /* initialize DMA addresses */
+ AFU_MF_PMD_DEBUG("src_addr: 0x%"PRIx64, ctx->src_iova);
+ rte_write64(SIZE_TO_CLS(ctx->src_iova), ctx->addr + CSR_SRC_ADDR);
+
+ AFU_MF_PMD_DEBUG("dst_addr: 0x%"PRIx64, ctx->dest_iova);
+ rte_write64(SIZE_TO_CLS(ctx->dest_iova), ctx->addr + CSR_DST_ADDR);
+
+ AFU_MF_PMD_DEBUG("dsm_addr: 0x%"PRIx64, ctx->dsm_iova);
+ rte_write32(SIZE_TO_CLS(ctx->dsm_iova), ctx->addr + CSR_AFU_DSM_BASEL);
+ rte_write32(SIZE_TO_CLS(ctx->dsm_iova) >> 32,
+ ctx->addr + CSR_AFU_DSM_BASEH);
+
+ ret = he_lbk_afu_config(dev);
+ if (ret)
+ return ret;
+
+ /* initialize src data */
+ ptr = (uint32_t *)ctx->src_ptr;
+ j = CLS_TO_SIZE(cfg->end) >> 2;
+ for (i = 0; i < j; i++)
+ *ptr++ = i;
+
+ /* start test */
+ for (cl = cfg->begin; cl <= cfg->end; cl += cfg->multi_cl) {
+ memset(ctx->dest_ptr, 0, CLS_TO_SIZE(cl));
+ memset(ctx->dsm_ptr, 0, DSM_SIZE);
+
+ ctl.csr = 0;
+ rte_write32(ctl.csr, ctx->addr + CSR_CTL);
+ rte_delay_us(1000);
+ ctl.reset = 1;
+ rte_write32(ctl.csr, ctx->addr + CSR_CTL);
+
+ rte_write32(cl - 1, ctx->addr + CSR_NUM_LINES);
+
+ ctl.start = 1;
+ rte_write32(ctl.csr, ctx->addr + CSR_CTL);
+
+ if (cfg->cont) {
+ rte_delay_ms(cfg->timeout * 1000);
+ ctl.force_completion = 1;
+ rte_write32(ctl.csr, ctx->addr + CSR_CTL);
+ ret = dsm_poll_timeout(&ctx->status_ptr->test_complete,
+ val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
+ DSM_TIMEOUT);
+ if (ret) {
+ printf("DSM poll timeout\n");
+ goto end;
+ }
+ } else {
+ ret = dsm_poll_timeout(&ctx->status_ptr->test_complete,
+ val, (val & 0x1) == 1, DSM_POLL_INTERVAL,
+ DSM_TIMEOUT);
+ if (ret) {
+ printf("DSM poll timeout\n");
+ goto end;
+ }
+ ctl.force_completion = 1;
+ rte_write32(ctl.csr, ctx->addr + CSR_CTL);
+ }
+
+ he_lbk_report(dev, cl);
+
+ i = 0;
+ while (i++ < 100) {
+ sval = rte_read64(ctx->addr + CSR_STATUS1);
+ if (sval == 0)
+ break;
+ rte_delay_us(1000);
+ }
+
+ if (cfg->mode == NLB_MODE_LPBK) {
+ ptr = (uint32_t *)ctx->dest_ptr;
+ j = CLS_TO_SIZE(cl) >> 2;
+ for (i = 0; i < j; i++) {
+ if (*ptr++ != i) {
+ AFU_MF_PMD_ERR("Data mismatch @ %u", i);
+ break;
+ }
+ }
+ }
+ }
+
+end:
+ return 0;
+}
+
+static int he_lbk_ctx_release(struct afu_mf_rawdev *dev)
+{
+ struct he_lbk_priv *priv = NULL;
+ struct he_lbk_ctx *ctx = NULL;
+
+ if (!dev)
+ return -EINVAL;
+
+ priv = (struct he_lbk_priv *)dev->priv;
+ if (!priv)
+ return -ENOENT;
+
+ ctx = &priv->he_lbk_ctx;
+
+ rte_free(ctx->dsm_ptr);
+ ctx->dsm_ptr = NULL;
+ ctx->status_ptr = NULL;
+
+ rte_free(ctx->src_ptr);
+ ctx->src_ptr = NULL;
+
+ rte_free(ctx->dest_ptr);
+ ctx->dest_ptr = NULL;
+
+ return 0;
+}
+
+static int he_lbk_ctx_init(struct afu_mf_rawdev *dev)
+{
+ struct he_lbk_priv *priv = NULL;
+ struct he_lbk_ctx *ctx = NULL;
+ int ret = 0;
+
+ if (!dev)
+ return -EINVAL;
+
+ priv = (struct he_lbk_priv *)dev->priv;
+ if (!priv)
+ return -ENOENT;
+
+ ctx = &priv->he_lbk_ctx;
+ ctx->addr = (uint8_t *)dev->addr;
+
+ ctx->dsm_ptr = (uint8_t *)rte_zmalloc(NULL, DSM_SIZE, TEST_MEM_ALIGN);
+ if (!ctx->dsm_ptr) {
+ ret = -ENOMEM;
+ goto release;
+ }
+ ctx->dsm_iova = rte_malloc_virt2iova(ctx->dsm_ptr);
+ if (ctx->dsm_iova == RTE_BAD_IOVA) {
+ ret = -ENOMEM;
+ goto release;
+ }
+
+ ctx->src_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
+ TEST_MEM_ALIGN);
+ if (!ctx->src_ptr) {
+ ret = -ENOMEM;
+ goto release;
+ }
+ ctx->src_iova = rte_malloc_virt2iova(ctx->src_ptr);
+ if (ctx->src_iova == RTE_BAD_IOVA) {
+ ret = -ENOMEM;
+ goto release;
+ }
+
+ ctx->dest_ptr = (uint8_t *)rte_zmalloc(NULL, NLB_BUF_SIZE,
+ TEST_MEM_ALIGN);
+ if (!ctx->dest_ptr) {
+ ret = -ENOMEM;
+ goto release;
+ }
+ ctx->dest_iova = rte_malloc_virt2iova(ctx->dest_ptr);
+ if (ctx->dest_iova == RTE_BAD_IOVA) {
+ ret = -ENOMEM;
+ goto release;
+ }
+
+ ctx->status_ptr = (struct he_lbk_dsm_status *)ctx->dsm_ptr;
+ return 0;
+
+release:
+ he_lbk_ctx_release(dev);
+ return ret;
+}
+
+static int he_lbk_init(struct afu_mf_rawdev *dev)
+{
+ if (!dev)
+ return -EINVAL;
+
+ if (!dev->priv) {
+ dev->priv = rte_zmalloc(NULL, sizeof(struct he_lbk_priv), 0);
+ if (!dev->priv)
+ return -ENOMEM;
+ }
+
+ return he_lbk_ctx_init(dev);
+}
+
+static int he_lbk_config(struct afu_mf_rawdev *dev, void *config,
+ size_t config_size)
+{
+ struct he_lbk_priv *priv = NULL;
+ struct rte_pmd_afu_he_lbk_cfg *cfg = NULL;
+
+ if (!dev || !config || !config_size)
+ return -EINVAL;
+
+ priv = (struct he_lbk_priv *)dev->priv;
+ if (!priv)
+ return -ENOENT;
+
+ if (config_size != sizeof(struct rte_pmd_afu_he_lbk_cfg))
+ return -EINVAL;
+
+ cfg = (struct rte_pmd_afu_he_lbk_cfg *)config;
+ if (cfg->mode > NLB_MODE_TRPUT)
+ return -EINVAL;
+ if ((cfg->multi_cl != 1) && (cfg->multi_cl != 2) &&
+ (cfg->multi_cl != 4))
+ return -EINVAL;
+ if ((cfg->begin < MIN_CACHE_LINES) || (cfg->begin > MAX_CACHE_LINES))
+ return -EINVAL;
+ if ((cfg->end < cfg->begin) || (cfg->end > MAX_CACHE_LINES))
+ return -EINVAL;
+
+ rte_memcpy(&priv->he_lbk_cfg, cfg, sizeof(priv->he_lbk_cfg));
+
+ return 0;
+}
+
+static int he_lbk_close(struct afu_mf_rawdev *dev)
+{
+ if (!dev)
+ return -EINVAL;
+
+ he_lbk_ctx_release(dev);
+
+ rte_free(dev->priv);
+ dev->priv = NULL;
+
+ return 0;
+}
+
+static int he_lbk_dump(struct afu_mf_rawdev *dev, FILE *f)
+{
+ struct he_lbk_priv *priv = NULL;
+ struct he_lbk_ctx *ctx = NULL;
+
+ if (!dev)
+ return -EINVAL;
+
+ priv = (struct he_lbk_priv *)dev->priv;
+ if (!priv)
+ return -ENOENT;
+
+ if (!f)
+ f = stdout;
+
+ ctx = &priv->he_lbk_ctx;
+
+ fprintf(f, "addr:\t\t%p\n", (void *)ctx->addr);
+ fprintf(f, "dsm_ptr:\t%p\n", (void *)ctx->dsm_ptr);
+ fprintf(f, "dsm_iova:\t0x%"PRIx64"\n", ctx->dsm_iova);
+ fprintf(f, "src_ptr:\t%p\n", (void *)ctx->src_ptr);
+ fprintf(f, "src_iova:\t0x%"PRIx64"\n", ctx->src_iova);
+ fprintf(f, "dest_ptr:\t%p\n", (void *)ctx->dest_ptr);
+ fprintf(f, "dest_iova:\t0x%"PRIx64"\n", ctx->dest_iova);
+ fprintf(f, "status_ptr:\t%p\n", (void *)ctx->status_ptr);
+
+ return 0;
+}
+
+static struct afu_mf_ops he_lbk_ops = {
+ .init = he_lbk_init,
+ .config = he_lbk_config,
+ .start = NULL,
+ .stop = NULL,
+ .test = he_lbk_test,
+ .close = he_lbk_close,
+ .dump = he_lbk_dump,
+ .reset = NULL
+};
+
+struct afu_mf_drv he_lbk_drv = {
+ .uuid = { HE_LBK_UUID_L, HE_LBK_UUID_H },
+ .ops = &he_lbk_ops
+};
+
+struct afu_mf_drv he_mem_lbk_drv = {
+ .uuid = { HE_MEM_LBK_UUID_L, HE_MEM_LBK_UUID_H },
+ .ops = &he_lbk_ops
+};
new file mode 100644
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Intel Corporation
+ */
+
+#ifndef _HE_LBK_H_
+#define _HE_LBK_H_
+
+#include "afu_mf_rawdev.h"
+#include "rte_pmd_afu.h"
+
+#define HE_LBK_UUID_L 0xb94b12284c31e02b
+#define HE_LBK_UUID_H 0x56e203e9864f49a7
+#define HE_MEM_LBK_UUID_L 0xbb652a578330a8eb
+#define HE_MEM_LBK_UUID_H 0x8568ab4e6ba54616
+
+extern struct afu_mf_drv he_lbk_drv;
+extern struct afu_mf_drv he_mem_lbk_drv;
+
+/* HE-LBK & HE-MEM-LBK registers definition */
+#define CSR_SCRATCHPAD0 0x100
+#define CSR_SCRATCHPAD1 0x108
+#define CSR_AFU_DSM_BASEL 0x110
+#define CSR_AFU_DSM_BASEH 0x114
+#define CSR_SRC_ADDR 0x120
+#define CSR_DST_ADDR 0x128
+#define CSR_NUM_LINES 0x130
+#define CSR_CTL 0x138
+#define CSR_CFG 0x140
+#define CSR_INACT_THRESH 0x148
+#define CSR_INTERRUPT0 0x150
+#define CSR_SWTEST_MSG 0x158
+#define CSR_STATUS0 0x160
+#define CSR_STATUS1 0x168
+#define CSR_ERROR 0x170
+#define CSR_STRIDE 0x178
+#define CSR_HE_INFO0 0x180
+
+#define DSM_SIZE 0x200000
+#define DSM_POLL_INTERVAL 5 /* ms */
+#define DSM_TIMEOUT 1000 /* ms */
+
+#define NLB_BUF_SIZE 0x400000
+#define TEST_MEM_ALIGN 1024
+
+struct he_lbk_csr_ctl {
+ union {
+ uint32_t csr;
+ struct {
+ uint32_t reset:1;
+ uint32_t start:1;
+ uint32_t force_completion:1;
+ uint32_t reserved:29;
+ };
+ };
+};
+
+struct he_lbk_csr_cfg {
+ union {
+ uint32_t csr;
+ struct {
+ uint32_t rsvd1:1;
+ uint32_t cont:1;
+ uint32_t mode:3;
+ uint32_t multicl_len:2;
+ uint32_t rsvd2:13;
+ uint32_t trput_interleave:3;
+ uint32_t test_cfg:5;
+ uint32_t interrupt_on_error:1;
+ uint32_t interrupt_testmode:1;
+ uint32_t rsvd3:2;
+ };
+ };
+};
+
+struct he_lbk_status0 {
+ union {
+ uint64_t csr;
+ struct {
+ uint32_t num_writes;
+ uint32_t num_reads;
+ };
+ };
+};
+
+struct he_lbk_status1 {
+ union {
+ uint64_t csr;
+ struct {
+ uint32_t num_pend_writes;
+ uint32_t num_pend_reads;
+ };
+ };
+};
+
+struct he_lbk_dsm_status {
+ uint32_t test_complete;
+ uint32_t test_error;
+ uint64_t num_clocks;
+ uint32_t num_reads;
+ uint32_t num_writes;
+ uint32_t start_overhead;
+ uint32_t end_overhead;
+};
+
+struct he_lbk_ctx {
+ uint8_t *addr;
+ uint8_t *dsm_ptr;
+ uint64_t dsm_iova;
+ uint8_t *src_ptr;
+ uint64_t src_iova;
+ uint8_t *dest_ptr;
+ uint64_t dest_iova;
+ struct he_lbk_dsm_status *status_ptr;
+};
+
+struct he_lbk_priv {
+ struct rte_pmd_afu_he_lbk_cfg he_lbk_cfg;
+ struct he_lbk_ctx he_lbk_ctx;
+};
+
+#endif /* _HE_LBK_H_ */
@@ -2,6 +2,6 @@
# Copyright 2022 Intel Corporation
deps += ['rawdev', 'bus_pci', 'bus_ifpga']
-sources = files('afu_mf_rawdev.c', 'n3000_afu.c')
+sources = files('afu_mf_rawdev.c', 'n3000_afu.c', 'he_lbk.c')
headers = files('rte_pmd_afu.h')
@@ -90,6 +90,20 @@ struct rte_pmd_afu_n3000_cfg {
};
};
+/**
+ * HE-LBK & HE-MEM-LBK AFU configuration data structure.
+ */
+struct rte_pmd_afu_he_lbk_cfg {
+ uint32_t mode;
+ uint32_t begin;
+ uint32_t end;
+ uint32_t multi_cl;
+ uint32_t cont;
+ uint32_t timeout;
+ uint32_t trput_interleave;
+ uint32_t freq_mhz;
+};
+
#ifdef __cplusplus
}
#endif