From patchwork Tue Apr 18 05:11:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenzhuo Lu X-Patchwork-Id: 126211 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D1B0C42977; Tue, 18 Apr 2023 07:43:08 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1A87942D16; Tue, 18 Apr 2023 07:43:05 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mails.dpdk.org (Postfix) with ESMTP id 1F46E40EDF for ; Tue, 18 Apr 2023 07:43:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681796583; x=1713332583; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=a7K2k4w8bhMFWQnZGfWuzZeZE341GX1Hg1oIhfiPkOg=; b=GjKgLnneJH8Isa0nAvTG2hZOaUHZKZe5s1dVu4vwsqaQo52qGqBj86Vk ykSRb2YQtwwGwzFyfG02Jjlyr20Cd5qmDgM3wUrnT0QzXP7QfnppjuP/R kqR4hccgglE281P8s3PBk3xE232OG63QGNFTYlADDPkP/v0Sb0C9r07tA TdUgGrH/UHCt5QW2oSsLbnE9auy2NI766R14MX62q5U+w/rmFjIGM1bS5 xzzQQbWFOsyrnmIACBV0mzvHRUiT6GsZ+jOHZlVjniIHOiJcdb742h9Yq qVp31s3usKDsSJFxmpSKzO42uLXe3KLgoO/w0e5uPdP6Lai3poyeIpDyp w==; X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="347830532" X-IronPort-AV: E=Sophos;i="5.99,206,1677571200"; d="scan'208";a="347830532" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Apr 2023 22:43:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10683"; a="937115687" X-IronPort-AV: E=Sophos;i="5.99,206,1677571200"; d="scan'208";a="937115687" Received: from dpdk-wenzhuo-cascadelake.sh.intel.com ([10.67.110.255]) by fmsmga006.fm.intel.com with ESMTP; 17 Apr 2023 22:43:01 -0700 From: Wenzhuo Lu To: dev@dpdk.org Cc: Wenzhuo Lu Subject: [PATCH 1/2] net/iavf: add Tx AVX2 offload path Date: Tue, 18 Apr 2023 13:11:05 +0800 Message-Id: <1681794666-68144-2-git-send-email-wenzhuo.lu@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1681794666-68144-1-git-send-email-wenzhuo.lu@intel.com> References: <1681794666-68144-1-git-send-email-wenzhuo.lu@intel.com> X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Add a specific path for TX AVX2. In this path, support the HW offload features, like, checksum insertion, VLAN insertion. This path is chosen automatically according to the configuration. 'inline' is used, then the duplicate code is generated by the compiler. Signed-off-by: Wenzhuo Lu --- drivers/net/iavf/iavf_rxtx.c | 33 ++++++++++------ drivers/net/iavf/iavf_rxtx.h | 2 + drivers/net/iavf/iavf_rxtx_vec_avx2.c | 54 +++++++++++++++++++-------- 3 files changed, 62 insertions(+), 27 deletions(-) diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c index b1d0fbceb6..6cadecfad9 100644 --- a/drivers/net/iavf/iavf_rxtx.c +++ b/drivers/net/iavf/iavf_rxtx.c @@ -3876,14 +3876,14 @@ iavf_set_tx_function(struct rte_eth_dev *dev) if (check_ret >= 0 && rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { - /* SSE and AVX2 not support offload path yet. */ + /* SSE not support offload path yet. */ if (check_ret == IAVF_VECTOR_PATH) { use_sse = true; - if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && - rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) - use_avx2 = true; } + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256) + use_avx2 = true; #ifdef CC_AVX512_SUPPORT if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 && rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1 && @@ -3894,15 +3894,24 @@ iavf_set_tx_function(struct rte_eth_dev *dev) if (!use_sse && !use_avx2 && !use_avx512) goto normal; - if (!use_avx512) { - PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).", - use_avx2 ? "avx2 " : "", + dev->tx_pkt_prepare = NULL; + if (use_sse) { + PMD_DRV_LOG(DEBUG, "Using Vector Tx (port %d).", dev->data->port_id); - dev->tx_pkt_burst = use_avx2 ? - iavf_xmit_pkts_vec_avx2 : - iavf_xmit_pkts_vec; + dev->tx_pkt_burst = iavf_xmit_pkts_vec; + } + if (use_avx2) { + if (check_ret == IAVF_VECTOR_PATH) { + dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx2; + PMD_DRV_LOG(DEBUG, "Using AVX2 Vector Tx (port %d).", + dev->data->port_id); + } else { + dev->tx_pkt_burst = iavf_xmit_pkts_vec_avx2_offload; + dev->tx_pkt_prepare = iavf_prep_pkts; + PMD_DRV_LOG(DEBUG, "Using AVX2 OFFLOAD Vector Tx (port %d).", + dev->data->port_id); + } } - dev->tx_pkt_prepare = NULL; #ifdef CC_AVX512_SUPPORT if (use_avx512) { if (check_ret == IAVF_VECTOR_PATH) { diff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h index 09e2127db0..85801160e1 100644 --- a/drivers/net/iavf/iavf_rxtx.h +++ b/drivers/net/iavf/iavf_rxtx.h @@ -693,6 +693,8 @@ uint16_t iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); uint16_t iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts); +uint16_t iavf_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts); int iavf_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc); int iavf_rx_vec_dev_check(struct rte_eth_dev *dev); int iavf_tx_vec_dev_check(struct rte_eth_dev *dev); diff --git a/drivers/net/iavf/iavf_rxtx_vec_avx2.c b/drivers/net/iavf/iavf_rxtx_vec_avx2.c index b4ebac9d34..c17b96008b 100644 --- a/drivers/net/iavf/iavf_rxtx_vec_avx2.c +++ b/drivers/net/iavf/iavf_rxtx_vec_avx2.c @@ -1426,30 +1426,32 @@ iavf_recv_scattered_pkts_vec_avx2_flex_rxd(void *rx_queue, rx_pkts + retval, nb_pkts); } -static inline void +static __rte_always_inline void iavf_vtx1(volatile struct iavf_tx_desc *txdp, - struct rte_mbuf *pkt, uint64_t flags) + struct rte_mbuf *pkt, uint64_t flags, bool offload) { uint64_t high_qw = (IAVF_TX_DESC_DTYPE_DATA | ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT) | ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)); + if (offload) + iavf_txd_enable_offload(pkt, &high_qw); __m128i descriptor = _mm_set_epi64x(high_qw, pkt->buf_iova + pkt->data_off); _mm_store_si128((__m128i *)txdp, descriptor); } -static inline void +static __rte_always_inline void iavf_vtx(volatile struct iavf_tx_desc *txdp, - struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags) + struct rte_mbuf **pkt, uint16_t nb_pkts, uint64_t flags, bool offload) { const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA | ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT)); /* if unaligned on 32-bit boundary, do one to align */ if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) { - iavf_vtx1(txdp, *pkt, flags); + iavf_vtx1(txdp, *pkt, flags, offload); nb_pkts--, txdp++, pkt++; } @@ -1459,18 +1461,26 @@ iavf_vtx(volatile struct iavf_tx_desc *txdp, hi_qw_tmpl | ((uint64_t)pkt[3]->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT); + if (offload) + iavf_txd_enable_offload(pkt[3], &hi_qw3); uint64_t hi_qw2 = hi_qw_tmpl | ((uint64_t)pkt[2]->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT); + if (offload) + iavf_txd_enable_offload(pkt[2], &hi_qw2); uint64_t hi_qw1 = hi_qw_tmpl | ((uint64_t)pkt[1]->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT); + if (offload) + iavf_txd_enable_offload(pkt[1], &hi_qw1); uint64_t hi_qw0 = hi_qw_tmpl | ((uint64_t)pkt[0]->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT); + if (offload) + iavf_txd_enable_offload(pkt[0], &hi_qw0); __m256i desc2_3 = _mm256_set_epi64x @@ -1490,14 +1500,14 @@ iavf_vtx(volatile struct iavf_tx_desc *txdp, /* do any last ones */ while (nb_pkts) { - iavf_vtx1(txdp, *pkt, flags); + iavf_vtx1(txdp, *pkt, flags, offload); txdp++, pkt++, nb_pkts--; } } -static inline uint16_t +static __rte_always_inline uint16_t iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, - uint16_t nb_pkts) + uint16_t nb_pkts, bool offload) { struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue; volatile struct iavf_tx_desc *txdp; @@ -1524,11 +1534,11 @@ iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, if (nb_commit >= n) { tx_backlog_entry(txep, tx_pkts, n); - iavf_vtx(txdp, tx_pkts, n - 1, flags); + iavf_vtx(txdp, tx_pkts, n - 1, flags, offload); tx_pkts += (n - 1); txdp += (n - 1); - iavf_vtx1(txdp, *tx_pkts++, rs); + iavf_vtx1(txdp, *tx_pkts++, rs, offload); nb_commit = (uint16_t)(nb_commit - n); @@ -1542,7 +1552,7 @@ iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, tx_backlog_entry(txep, tx_pkts, nb_commit); - iavf_vtx(txdp, tx_pkts, nb_commit, flags); + iavf_vtx(txdp, tx_pkts, nb_commit, flags, offload); tx_id = (uint16_t)(tx_id + nb_commit); if (tx_id > txq->next_rs) { @@ -1560,9 +1570,9 @@ iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, return nb_pkts; } -uint16_t -iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, - uint16_t nb_pkts) +static __rte_always_inline uint16_t +iavf_xmit_pkts_vec_avx2_common(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts, bool offload) { uint16_t nb_tx = 0; struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue; @@ -1573,7 +1583,7 @@ iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, /* cross rs_thresh boundary is not allowed */ num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh); ret = iavf_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx], - num); + num, offload); nb_tx += ret; nb_pkts -= ret; if (ret < num) @@ -1582,3 +1592,17 @@ iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, return nb_tx; } + +uint16_t +iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts) +{ + return iavf_xmit_pkts_vec_avx2_common(tx_queue, tx_pkts, nb_pkts, false); +} + +uint16_t +iavf_xmit_pkts_vec_avx2_offload(void *tx_queue, struct rte_mbuf **tx_pkts, + uint16_t nb_pkts) +{ + return iavf_xmit_pkts_vec_avx2_common(tx_queue, tx_pkts, nb_pkts, true); +}