From patchwork Wed Apr 24 13:21:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anatoly Burakov X-Patchwork-Id: 139662 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 298B443EAD; Wed, 24 Apr 2024 15:24:17 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C575434DC; Wed, 24 Apr 2024 15:22:56 +0200 (CEST) Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by mails.dpdk.org (Postfix) with ESMTP id 596B9434BC for ; Wed, 24 Apr 2024 15:22:53 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713964974; x=1745500974; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nk4D9SUBDAfWvFzTKQ2Sx3ixpH/Y8PPIkUKqRhAn3zo=; b=Q9TYdKJ3akc2HqD816tQEPdkarMXJ0fCwabMRcfdbOSPQVbtb8dei26T zJ5AehFo5I0Vur9PwzAbcofGfsLOukf1fIgT00f8rwTlxxA9Q6B4gEZXw 6vZ0HeNS8v7DPIojA7JWmCNTckLtL0GybkFjqe9gDrQugBT0FS4J43XK3 k1uYUo3RJmZi28peHQhErbXleiNE5iAfVCSPEgtg0jXGewW8Nt1QPhYkM ESrj9FGZpI2DzI8CLXzU0Mhw5GDMgzAqzl0XBfO0oUx8iBnd9ASG4sRXP 2Jm0iAz3LHXKwUaRTq4rgDGHXyKpQ4SqSwaMOtyIQAogCdebjoRD6vG2/ w==; X-CSE-ConnectionGUID: Oml1t941RzyIMSrBzPMQ4w== X-CSE-MsgGUID: HNRo+fE4S7OiZMGm2RYwMg== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="20289283" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="20289283" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 06:22:53 -0700 X-CSE-ConnectionGUID: dJMX7Qw/TGO6k75cBVGHjA== X-CSE-MsgGUID: fgLKlfPaSlKa7V4qhEpWPw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="24749484" Received: from silpixa00401119.ir.intel.com ([10.55.129.167]) by fmviesa006.fm.intel.com with ESMTP; 24 Apr 2024 06:22:51 -0700 From: Anatoly Burakov To: dev@dpdk.org Cc: Barbara Skobiej , vladimir.medvedkin@intel.com, bruce.richardson@intel.com, Jan Sokolowski Subject: [PATCH v1 17/22] net/ixgbe/base: add missing QV defines Date: Wed, 24 Apr 2024 14:21:51 +0100 Message-ID: <1cceb0254215479dea2d8b7eb0ecbc0e499967ef.1713964708.git.anatoly.burakov@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Barbara Skobiej This patch adds missing QV defines: - offset of ANVM data - Immediate Field module pointer offset - 2.5GBASE-T and 5GBASE-T physical layer types for X550 Signed-off-by: Barbara Skobiej Signed-off-by: Jan Sokolowski --- drivers/net/ixgbe/base/ixgbe_type.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h index 5bf03a1f62..9fed8b005c 100644 --- a/drivers/net/ixgbe/base/ixgbe_type.h +++ b/drivers/net/ixgbe/base/ixgbe_type.h @@ -3072,6 +3072,7 @@ enum ixgbe_fdir_pballoc_type { #define FW_SHADOW_RAM_DUMP_LEN 0 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ #define FW_NVM_DATA_OFFSET 3 +#define FW_ANVM_DATA_OFFSET 3 #define FW_MAX_READ_BUFFER_SIZE 1024 #define FW_DISABLE_RXEN_CMD 0xDE #define FW_DISABLE_RXEN_LEN 0x1 @@ -3143,6 +3144,8 @@ enum ixgbe_fdir_pballoc_type { #define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u #define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu +#define IXGBE_SR_IMMEDIATE_VALUES_PTR 0x4E + /* Host Interface Command Structures */ #pragma pack(push, 1) @@ -3446,6 +3449,8 @@ typedef u64 ixgbe_physical_layer; #define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x04000 #define IXGBE_PHYSICAL_LAYER_10BASE_T 0x08000 #define IXGBE_PHYSICAL_LAYER_2500BASE_KX 0x10000 +#define IXGBE_PHYSICAL_LAYER_2500BASE_T 0x20000 +#define IXGBE_PHYSICAL_LAYER_5000BASE_T 0x40000 /* Flow Control Data Sheet defined values * Calculation and defines taken from 802.1bb Annex O