From patchwork Thu Jul 13 05:36:49 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "De Lara Guarch, Pablo" X-Patchwork-Id: 26894 X-Patchwork-Delegate: pablo.de.lara.guarch@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id DCFF47CB9; Thu, 13 Jul 2017 15:37:05 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 8EBFB58F6; Thu, 13 Jul 2017 15:37:00 +0200 (CEST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jul 2017 06:37:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,354,1496127600"; d="scan'208";a="124713882" Received: from silpixa00399464.ir.intel.com (HELO silpixa00399464.ger.corp.intel.com) ([10.237.222.157]) by orsmga005.jf.intel.com with ESMTP; 13 Jul 2017 06:36:58 -0700 From: Pablo de Lara To: declan.doherty@intel.com, fiona.trahe@intel.com, john.griffin@intel.com, deepak.k.jain@intel.com Cc: dev@dpdk.org, Pablo de Lara , stable@dpdk.org Date: Thu, 13 Jul 2017 06:36:49 +0100 Message-Id: <20170713053650.62998-5-pablo.de.lara.guarch@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170713053650.62998-1-pablo.de.lara.guarch@intel.com> References: <20170713053650.62998-1-pablo.de.lara.guarch@intel.com> Subject: [dpdk-dev] [PATCH 4/5] doc: add missing algorithm in limitations for QAT X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For KASUMI, SNOW3G and ZUC algorithms, offsets and lengths of the data to cipher or authenticate is provided in bits, but QAT does not support non-byte aligned values, although only KASUMI and SNOW3G were mentioned. Fixes: d9b7d5bbc845 ("crypto/qat: add ZUC EEA3/EIA3 capability") Cc: stable@dpdk.org Signed-off-by: Pablo de Lara --- doc/guides/cryptodevs/qat.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst index 7a510c9..8e390ee 100644 --- a/doc/guides/cryptodevs/qat.rst +++ b/doc/guides/cryptodevs/qat.rst @@ -85,8 +85,8 @@ Limitations ----------- * Only supports the session-oriented API implementation (session-less APIs are not supported). -* SNOW 3G (UEA2) and KASUMI (F8) supported only if cipher length, cipher offset fields are byte-aligned. -* SNOW 3G (UIA2) and KASUMI (F9) supported only if hash length, hash offset fields are byte-aligned. +* SNOW 3G (UEA2), KASUMI (F8) and ZUC (EEA3) supported only if cipher length, cipher offset fields are byte-aligned. +* SNOW 3G (UIA2), KASUMI (F9) and ZUC (EIA3) supported only if hash length, hash offset fields are byte-aligned. * No BSD support as BSD QAT kernel driver not available. * ZUC EEA3/EIA3 is not supported by dh895xcc devices * Maximum additional authenticated data (AAD) for GCM is 240 bytes long.