diff mbox

[dpdk-dev,v1,5/7] net/mlx5: match Rx completion entry size to cacheline

Message ID 20171005230032.7548-6-yskoh@mellanox.com (mailing list archive)
State Superseded, archived
Delegated to: Ferruh Yigit
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail apply patch file failure

Commit Message

Yongseok Koh Oct. 5, 2017, 11 p.m. UTC 
  The size of Rx completion entry should match the size of a cacheline. This
is already reflected in struct mlx5_cqe by adding 64bytes padding if a
cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline.

Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
---
 drivers/net/mlx5/mlx5.c | 3 +++
 1 file changed, 3 insertions(+)

Comments

Nélio Laranjeiro Oct. 6, 2017, 7:55 a.m. UTC | #1 
On Thu, Oct 05, 2017 at 04:00:30PM -0700, Yongseok Koh wrote:
> The size of Rx completion entry should match the size of a cacheline. This
> is already reflected in struct mlx5_cqe by adding 64bytes padding if a
> cacheline is 128bytes. Some ARM CPUs have 128bytes cacheline.
> 
> Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
diff mbox

Patch

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 3362200c8..c23ce11f7 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1012,6 +1012,9 @@  rte_mlx5_pmd_init(void)
 	setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
 	/* Don't map UAR to WC if BlueFlame is not used.*/
 	setenv("MLX5_SHUT_UP_BF", "1", 1);
+	/* Match the size of Rx completion entry to the size of a cacheline. */
+	if (RTE_CACHE_LINE_SIZE == 128)
+		setenv("MLX5_CQE_SIZE", "128", 0);
 	ibv_fork_init();
 	rte_pci_register(&mlx5_driver);
 }