From patchwork Thu Jun 7 09:43:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Krawczyk X-Patchwork-Id: 40729 X-Patchwork-Delegate: ferruh.yigit@amd.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7830D1B3DF; Thu, 7 Jun 2018 11:43:58 +0200 (CEST) Received: from mail-lf0-f67.google.com (mail-lf0-f67.google.com [209.85.215.67]) by dpdk.org (Postfix) with ESMTP id 12A001B3D3 for ; Thu, 7 Jun 2018 11:43:55 +0200 (CEST) Received: by mail-lf0-f67.google.com with SMTP id i15-v6so3338248lfc.2 for ; Thu, 07 Jun 2018 02:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YkMoZ3ehthKuZvPEQPQJfZ+55VUJdGkxC1FGdwTPkM4=; b=ci/G+2zv1/COEdv8Io6kr4g4OC8mcky9K7h9P58hFSJ7obFe+1zfaOysr+ApiDpFPj M0I2pqM5Rq22MEFBFFo2GTyM7VcigKDckBEH1v1C60yIN2U7FdpbcZiJ/DvZJoQ25NWG /pdJiRq9JoV7D+TVCTdTXFxSqAEDomdFC3bppvNS6BpDm64eGVbDLJN0AObUbAAo9g9F mUyfmOeotObrBs9Iz/OOA6adH8fTzwIR7TzoeRN2gTsZ6yF8z7V9Fv+2kA3HCS50fzHs W4P92Mxu3gu9erQqNsrx/8JilZdbQ8FxGguF19MQZO8uNeCOqHIm+K80fqXjW1wfwiT/ Z9TQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YkMoZ3ehthKuZvPEQPQJfZ+55VUJdGkxC1FGdwTPkM4=; b=um4eeK83Z9DKay2jYWTtWuRD+CNJ3PBmfb+T4wkHP7poVlweTV4LFz+lI5liuD8E9R 0RjZ/QXZb3r+BRC+QO+ZK8mxeq8n39H+hK5WpHBaYz5+gpKXRjZVm62r4iJHHETHJ89m W39MQRTpz40jOtyu8HbvIItk+nsXWMwd/2f5ycgVNv0JyBmYYANekU/YUqvsh+So3+Wx rQhWeMwCLdFssaRpmY7ud3q7Q0/STyy8M6qilGUCVLqvcVK7zA3dHFsMNJXloT9+2zsT ZUreRvkvjwAzdfgnuKeer77JDesczGCJ/Ai5t0yQlX9igv6vEDLPEJIRVqLpnnvssRWN OzrA== X-Gm-Message-State: APt69E1NrfjXq0KoUJhmnLQLMwwHkA9Wa0U450Bn7KfGGXGejhkSgpXw TMy2Auy9RdI5DtD+vPEQ6m1FnA== X-Google-Smtp-Source: ADUXVKLg4N6nelH4CjYNV03K26u+fmt7YrQp+Byre9iFmciesPcguALYgqxVLR4WKxkCqO+ixugPng== X-Received: by 2002:a19:9358:: with SMTP id v85-v6mr817215lfd.83.1528364634758; Thu, 07 Jun 2018 02:43:54 -0700 (PDT) Received: from mkPC.semihalf.local (31-172-191-173.noc.fibertech.net.pl. [31.172.191.173]) by smtp.gmail.com with ESMTPSA id p28-v6sm3612368lfh.24.2018.06.07.02.43.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 07 Jun 2018 02:43:53 -0700 (PDT) From: Michal Krawczyk To: Marcin Wojtas , Michal Krawczyk , Guy Tzalik , Evgeny Schemeilin Cc: dev@dpdk.org, matua@amazon.com, Rafal Kozik Date: Thu, 7 Jun 2018 11:43:11 +0200 Message-Id: <20180607094322.14312-16-mk@semihalf.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180607094322.14312-1-mk@semihalf.com> References: <20180607094322.14312-1-mk@semihalf.com> Subject: [dpdk-dev] [PATCH v3 16/27] net/ena: add info about max number of Tx/Rx descriptors X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Rafal Kozik In function ena_infos_get driver provides information about minimal and maximal number of Rx and Tx descriptors. Signed-off-by: Rafal Kozik Acked-by: Michal Krawczyk --- drivers/net/ena/ena_ethdev.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c index cdefcd325..a88de2eca 100644 --- a/drivers/net/ena/ena_ethdev.c +++ b/drivers/net/ena/ena_ethdev.c @@ -85,6 +85,9 @@ #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define ENA_MAX_RING_DESC ENA_DEFAULT_RING_SIZE +#define ENA_MIN_RING_DESC 128 + enum ethtool_stringset { ETH_SS_TEST = 0, ETH_SS_STATS, @@ -1740,6 +1743,16 @@ static void ena_infos_get(struct rte_eth_dev *dev, adapter->tx_supported_offloads = tx_feat; adapter->rx_supported_offloads = rx_feat; + + dev_info->rx_desc_lim.nb_max = ENA_MAX_RING_DESC; + dev_info->rx_desc_lim.nb_min = ENA_MIN_RING_DESC; + + dev_info->tx_desc_lim.nb_max = ENA_MAX_RING_DESC; + dev_info->tx_desc_lim.nb_min = ENA_MIN_RING_DESC; + dev_info->tx_desc_lim.nb_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, + feat.max_queues.max_packet_tx_descs); + dev_info->tx_desc_lim.nb_mtu_seg_max = RTE_MIN(ENA_PKT_MAX_BUFS, + feat.max_queues.max_packet_tx_descs); } static uint16_t eth_ena_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,