diff --git a/drivers/event/octeontx2/otx2_evdev.c b/drivers/event/octeontx2/otx2_evdev.c
index 94c97fc9e..a6bf861fb 100644
--- a/drivers/event/octeontx2/otx2_evdev.c
+++ b/drivers/event/octeontx2/otx2_evdev.c
@@ -144,6 +144,12 @@ sso_lf_cfg(struct otx2_sso_evdev *dev, struct otx2_mbox *mbox,
 	return 0;
 }
 
+static void
+otx2_sso_port_release(void *port)
+{
+	rte_free(port);
+}
+
 static void
 otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
 {
@@ -151,13 +157,24 @@ otx2_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id)
 	RTE_SET_USED(queue_id);
 }
 
+static void
+sso_set_port_ops(struct otx2_ssogws *ws, uintptr_t base)
+{
+	ws->tag_op		= base + SSOW_LF_GWS_TAG;
+	ws->wqp_op		= base + SSOW_LF_GWS_WQP;
+	ws->getwrk_op		= base + SSOW_LF_GWS_OP_GET_WORK;
+	ws->swtp_op		= base + SSOW_LF_GWS_SWTP;
+	ws->swtag_norm_op	= base + SSOW_LF_GWS_OP_SWTAG_NORM;
+	ws->swtag_desched_op	= base + SSOW_LF_GWS_OP_SWTAG_DESCHED;
+}
+
 static int
 sso_configure_ports(const struct rte_eventdev *event_dev)
 {
 	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
 	struct otx2_mbox *mbox = dev->mbox;
 	uint8_t nb_lf;
-	int rc;
+	int i, rc;
 
 	otx2_sso_dbg("Configuring event ports %d", dev->nb_event_ports);
 
@@ -175,6 +192,40 @@ sso_configure_ports(const struct rte_eventdev *event_dev)
 		return -ENODEV;
 	}
 
+	for (i = 0; i < nb_lf; i++) {
+		struct otx2_ssogws *ws;
+		uintptr_t base;
+
+		/* Free memory prior to re-allocation if needed */
+		if (event_dev->data->ports[i] != NULL) {
+			ws = event_dev->data->ports[i];
+			rte_free(ws);
+			ws = NULL;
+		}
+
+		/* Allocate event port memory */
+		ws = rte_zmalloc_socket("otx2_sso_ws",
+					sizeof(struct otx2_ssogws),
+					RTE_CACHE_LINE_SIZE,
+					event_dev->data->socket_id);
+		if (ws == NULL) {
+			otx2_err("Failed to alloc memory for port=%d", i);
+			rc = -ENOMEM;
+			break;
+		}
+
+		ws->port = i;
+		base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20 | i << 12);
+		sso_set_port_ops(ws, base);
+
+		event_dev->data->ports[i] = ws;
+	}
+
+	if (rc < 0) {
+		sso_lf_cfg(dev, mbox, SSO_LF_GWS, nb_lf, false);
+		sso_hw_lf_cfg(mbox, SSO_LF_GWS, nb_lf, false);
+	}
+
 	return rc;
 }
 
@@ -459,6 +510,60 @@ otx2_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
 	return 0;
 }
 
+static void
+otx2_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
+		       struct rte_event_port_conf *port_conf)
+{
+	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+
+	RTE_SET_USED(port_id);
+	port_conf->new_event_threshold = dev->max_num_events;
+	port_conf->dequeue_depth = 1;
+	port_conf->enqueue_depth = 1;
+}
+
+static int
+otx2_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
+		    const struct rte_event_port_conf *port_conf)
+{
+	struct otx2_sso_evdev *dev = sso_pmd_priv(event_dev);
+	uintptr_t grps_base[OTX2_SSO_MAX_VHGRP] = {0};
+	uint64_t val;
+	uint16_t q;
+
+	sso_func_trace("Port=%d", port_id);
+	RTE_SET_USED(port_conf);
+
+	if (event_dev->data->ports[port_id] == NULL) {
+		otx2_err("Invalid port Id %d", port_id);
+		return -EINVAL;
+	}
+
+	for (q = 0; q < dev->nb_event_queues; q++) {
+		grps_base[q] = dev->bar2 + (RVU_BLOCK_ADDR_SSO << 20 | q << 12);
+		if (grps_base[q] == 0) {
+			otx2_err("Failed to get grp[%d] base addr", q);
+			return -EINVAL;
+		}
+	}
+
+	/* Set get_work timeout for HWS */
+	val = NSEC2USEC(dev->deq_tmo_ns) - 1;
+
+	struct otx2_ssogws *ws = event_dev->data->ports[port_id];
+	uintptr_t base = OTX2_SSOW_GET_BASE_ADDR(ws->getwrk_op);
+
+	rte_memcpy(ws->grps_base, grps_base,
+		   sizeof(uintptr_t) * OTX2_SSO_MAX_VHGRP);
+	ws->fc_mem = dev->fc_mem;
+	ws->xaq_lmt = dev->xaq_lmt;
+	otx2_write64(val, base + SSOW_LF_GWS_NW_TIM);
+
+	otx2_sso_dbg("Port=%d ws=%p", port_id, event_dev->data->ports[port_id]);
+
+	return 0;
+}
+
 /* Initialize and register event driver with DPDK Application */
 static struct rte_eventdev_ops otx2_sso_ops = {
 	.dev_infos_get    = otx2_sso_info_get,
@@ -466,6 +571,9 @@ static struct rte_eventdev_ops otx2_sso_ops = {
 	.queue_def_conf   = otx2_sso_queue_def_conf,
 	.queue_setup      = otx2_sso_queue_setup,
 	.queue_release    = otx2_sso_queue_release,
+	.port_def_conf    = otx2_sso_port_def_conf,
+	.port_setup       = otx2_sso_port_setup,
+	.port_release     = otx2_sso_port_release,
 };
 
 #define OTX2_SSO_XAE_CNT	"xae_cnt"
diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h
index acc8b6b3e..3f4931ff1 100644
--- a/drivers/event/octeontx2/otx2_evdev.h
+++ b/drivers/event/octeontx2/otx2_evdev.h
@@ -38,6 +38,42 @@
 #define SSO_LF_GGRP_AQ_THR                  (0x1e0ull)
 #define SSO_LF_GGRP_MISC_CNT                (0x200ull)
 
+/* SSOW LF register offsets (BAR2) */
+#define SSOW_LF_GWS_LINKS                   (0x10ull)
+#define SSOW_LF_GWS_PENDWQP                 (0x40ull)
+#define SSOW_LF_GWS_PENDSTATE               (0x50ull)
+#define SSOW_LF_GWS_NW_TIM                  (0x70ull)
+#define SSOW_LF_GWS_GRPMSK_CHG              (0x80ull)
+#define SSOW_LF_GWS_INT                     (0x100ull)
+#define SSOW_LF_GWS_INT_W1S                 (0x108ull)
+#define SSOW_LF_GWS_INT_ENA_W1S             (0x110ull)
+#define SSOW_LF_GWS_INT_ENA_W1C             (0x118ull)
+#define SSOW_LF_GWS_TAG                     (0x200ull)
+#define SSOW_LF_GWS_WQP                     (0x210ull)
+#define SSOW_LF_GWS_SWTP                    (0x220ull)
+#define SSOW_LF_GWS_PENDTAG                 (0x230ull)
+#define SSOW_LF_GWS_OP_ALLOC_WE             (0x400ull)
+#define SSOW_LF_GWS_OP_GET_WORK             (0x600ull)
+#define SSOW_LF_GWS_OP_SWTAG_FLUSH          (0x800ull)
+#define SSOW_LF_GWS_OP_SWTAG_UNTAG          (0x810ull)
+#define SSOW_LF_GWS_OP_SWTP_CLR             (0x820ull)
+#define SSOW_LF_GWS_OP_UPD_WQP_GRP0         (0x830ull)
+#define SSOW_LF_GWS_OP_UPD_WQP_GRP1         (0x838ull)
+#define SSOW_LF_GWS_OP_DESCHED              (0x880ull)
+#define SSOW_LF_GWS_OP_DESCHED_NOSCH        (0x8c0ull)
+#define SSOW_LF_GWS_OP_SWTAG_DESCHED        (0x980ull)
+#define SSOW_LF_GWS_OP_SWTAG_NOSCHED        (0x9c0ull)
+#define SSOW_LF_GWS_OP_CLR_NSCHED0          (0xa00ull)
+#define SSOW_LF_GWS_OP_CLR_NSCHED1          (0xa08ull)
+#define SSOW_LF_GWS_OP_SWTP_SET             (0xc00ull)
+#define SSOW_LF_GWS_OP_SWTAG_NORM           (0xc10ull)
+#define SSOW_LF_GWS_OP_SWTAG_FULL0          (0xc20ull)
+#define SSOW_LF_GWS_OP_SWTAG_FULL1          (0xc28ull)
+#define SSOW_LF_GWS_OP_GWC_INVAL            (0xe00ull)
+
+#define OTX2_SSOW_GET_BASE_ADDR(_GW)        ((_GW) - SSOW_LF_GWS_OP_GET_WORK)
+
+#define NSEC2USEC(__ns)			((__ns) / 1E3)
 #define USEC2NSEC(__us)                 ((__us) * 1E3)
 
 enum otx2_sso_lf_type {
@@ -70,6 +106,29 @@ struct otx2_sso_evdev {
 	uint32_t iue;
 } __rte_cache_aligned;
 
+#define OTX2_SSOGWS_OPS \
+	/* WS ops */			\
+	uintptr_t getwrk_op;		\
+	uintptr_t tag_op;		\
+	uintptr_t wqp_op;		\
+	uintptr_t swtp_op;		\
+	uintptr_t swtag_norm_op;	\
+	uintptr_t swtag_desched_op;	\
+	uint8_t cur_tt;			\
+	uint8_t cur_grp
+
+/* Event port aka GWS */
+struct otx2_ssogws {
+	/* Get Work Fastpath data */
+	OTX2_SSOGWS_OPS;
+	uint8_t swtag_req;
+	uint8_t port;
+	/* Add Work Fastpath data */
+	uint64_t xaq_lmt __rte_cache_aligned;
+	uint64_t *fc_mem;
+	uintptr_t grps_base[OTX2_SSO_MAX_VHGRP];
+} __rte_cache_aligned;
+
 static inline struct otx2_sso_evdev *
 sso_pmd_priv(const struct rte_eventdev *event_dev)
 {
