From patchwork Thu May 7 08:58:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerin Jacob Kollanukkaran X-Patchwork-Id: 69912 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 671DCA00C5; Thu, 7 May 2020 10:57:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 227B01DB19; Thu, 7 May 2020 10:57:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 3C7E11DB0C for ; Thu, 7 May 2020 10:57:06 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0478uNXn008171; Thu, 7 May 2020 01:57:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=bXKEvnRQDEModYwKBPEwq5ELAdza2/F4NMnhbJlxR24=; b=hhMT/ZCVipwu+j/dCvVy2l1e8zJUHzcjPkFPGwFAHSVVJX+9mh/GgbZ+CHt95mnhh6md 5AvtuNvkQ0T50EKQvJ0HdPgHXdVxX1w3uzVj0QJ/QYGUaUnIFky5qjqpycxrDW7V18vq 4QvgMGGlfOQjv0pEKthBuH1dLvGkZkkWppl/PZpgY1U5fN0U7gU+aPFIw5UYb5g2SWBx QtJFf2rj6VzrllQR3oJst1vZeAcRFTu8AEgkvWv+ewYfV3uGltCLCnPTqGv4nyyaCaPt ggybH0jyfPFZ1kBRQFzbyJeplrm7koXyMpHFUAd8K0C3uhC7PEyef1FzuA2K2HnHZUZs 0w== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 30uaum1ejs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 07 May 2020 01:57:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 7 May 2020 01:57:03 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 7 May 2020 01:57:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 7 May 2020 01:57:03 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id B3ACE3F703F; Thu, 7 May 2020 01:57:01 -0700 (PDT) From: To: Jerin Jacob , Nithin Dabilpuram CC: , Date: Thu, 7 May 2020 14:28:07 +0530 Message-ID: <20200507085807.1746539-1-jerinj@marvell.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216, 18.0.676 definitions=2020-05-07_05:2020-05-05, 2020-05-07 signatures=0 Subject: [dpdk-dev] [PATCH] common/octeontx2: upgrade mbox definition to version 7 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Upgrade mailbox definitions to version 0x0007 of kernel AF driver. Signed-off-by: Jerin Jacob --- drivers/common/octeontx2/otx2_mbox.h | 39 ++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/drivers/common/octeontx2/otx2_mbox.h b/drivers/common/octeontx2/otx2_mbox.h index 5351deaf2..80778a0be 100644 --- a/drivers/common/octeontx2/otx2_mbox.h +++ b/drivers/common/octeontx2/otx2_mbox.h @@ -90,7 +90,7 @@ struct mbox_msghdr { #define OTX2_MBOX_RSP_SIG (0xbeef) /* Signature, for validating corrupted msgs */ uint16_t __otx2_io sig; -#define OTX2_MBOX_VERSION (0x0006) +#define OTX2_MBOX_VERSION (0x0007) /* Version of msg's structure for this ID */ uint16_t __otx2_io ver; /* Offset of next msg within mailbox region */ @@ -150,6 +150,8 @@ M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \ M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\ cgx_set_link_mode_rsp) \ +M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ +M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \ /* NPA mbox IDs (range 0x400 - 0x5FF) */ \ M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \ npa_lf_alloc_rsp) \ @@ -352,9 +354,20 @@ struct npc_set_pkind { /* Structure for requesting resource provisioning. * 'modify' flag to be used when either requesting more - * or detach partial of a certain resource type. + * or to detach partial of a certain resource type. * Rest of the fields specify how many of what type to * be attached. + * To request LFs from two blocks of same type this mailbox + * can be sent twice as below: + * struct rsrc_attach *attach; + * .. Allocate memory for message .. + * attach->cptlfs = 3; <3 LFs from CPT0> + * .. Send message .. + * .. Allocate memory for message .. + * attach->modify = 1; + * attach->cpt_blkaddr = BLKADDR_CPT1; + * attach->cptlfs = 2; <2 LFs from CPT1> + * .. Send message .. */ struct rsrc_attach_req { struct mbox_msghdr hdr; @@ -365,6 +378,11 @@ struct rsrc_attach_req { uint16_t __otx2_io ssow; uint16_t __otx2_io timlfs; uint16_t __otx2_io cptlfs; + uint16_t __otx2_io reelfs; + /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */ + int __otx2_io cpt_blkaddr; + /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */ + int __otx2_io ree_blkaddr; }; /* Structure for relinquishing resources. @@ -381,6 +399,7 @@ struct rsrc_detach_req { uint8_t __otx2_io ssow:1; uint8_t __otx2_io timlfs:1; uint8_t __otx2_io cptlfs:1; + uint8_t __otx2_io reelfs:1; }; /* NIX Transmit schedulers */ @@ -405,6 +424,11 @@ struct free_rsrcs_rsp { uint16_t __otx2_io cpt; uint8_t __otx2_io npa; uint8_t __otx2_io nix; + uint16_t __otx2_io schq_nix1[NIX_TXSCH_LVL_CNT]; + uint8_t __otx2_io nix1; + uint8_t __otx2_io cpt1; + uint8_t __otx2_io ree0; + uint8_t __otx2_io ree1; }; #define MSIX_VECTOR_INVALID 0xFFFF @@ -422,6 +446,13 @@ struct msix_offset_rsp { uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT]; uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT]; uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT]; + uint8_t __otx2_io cpt1_lfs; + uint8_t __otx2_io ree0_lfs; + uint8_t __otx2_io ree1_lfs; + uint16_t __otx2_io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT]; + uint16_t __otx2_io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT]; + uint16_t __otx2_io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT]; + }; /* CGX mbox message formats */ @@ -732,6 +763,9 @@ struct nix_lf_alloc_rsp { uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */ uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */ uint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */ + uint8_t __otx2_io cgx_links; /* No. of CGX links present in HW */ + uint8_t __otx2_io lbk_links; /* No. of LBK links present in HW */ + uint8_t __otx2_io sdp_links; /* No. of SDP links present in HW */ }; struct nix_lf_free_req { @@ -1393,6 +1427,7 @@ enum header_fields { NPC_DPORT_TCP, NPC_SPORT_UDP, NPC_DPORT_UDP, + NPC_FDSA_VAL, NPC_HEADER_FIELDS_MAX, };