From patchwork Sat Mar 6 16:29:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 88654 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EBF8FA0548; Sat, 6 Mar 2021 17:32:06 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B3B5722A4A0; Sat, 6 Mar 2021 17:30:56 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4866922A4A0 for ; Sat, 6 Mar 2021 17:30:54 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 126GUnq4006404 for ; Sat, 6 Mar 2021 08:30:53 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=76+ZpnMBSLZYv+/NoTlu4wose88atrdVfAcz1qnv9V8=; b=UAWpRWIe1T70WVzbSU31gWwz4QGmMNNoCyV7QozoqhYRfTBFEna5+YjNMvMZmXyzpO+F l32MBYc8eEbsAm0L34kbzd3tGjJEd8u0wt5I4qyE8ZbuQC7/iz+3KuDtXUbMrsChL3yW u6dv+vjsNb5zZdhotCzK7Y1TikysYe5m0iPGKIfSBv3zu336/RLc0TY7Evrp2OgwGLXA XJFg3Oe2yixheDY3b9dYxGgheyG1MJBe91zkJki7tooy2DMxDyY8QzDxzsbMMtUoPBls S+ly4JLq11O2gOpTUc48tfiYSZh02Fvr2z8z5WUbFteAIRQ2Glpw6EmW1FCVVh/UQLzK 1g== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3747yurew8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 06 Mar 2021 08:30:53 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Mar 2021 08:30:52 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 6 Mar 2021 08:30:52 -0800 Received: from BG-LT7430.marvell.com (unknown [10.193.68.121]) by maili.marvell.com (Postfix) with ESMTP id 2AF513F7041; Sat, 6 Mar 2021 08:30:49 -0800 (PST) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: , Date: Sat, 6 Mar 2021 21:59:17 +0530 Message-ID: <20210306162942.6845-13-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210306162942.6845-1-pbhagavatula@marvell.com> References: <20210306162942.6845-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-06_08:2021-03-03, 2021-03-06 signatures=0 Subject: [dpdk-dev] [PATCH 12/36] event/cnxk: add devargs to configure getwork mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add devargs to configure the platform specific getwork mode. CN9K getwork mode by default is set to use dual workslot mode. Add option to force single workslot mode. Example: --dev "0002:0e:00.0,single_ws=1" CN10K supports multiple getwork prefetch modes, by default the prefetch mode is set to none. Add option to select getwork prefetch mode Example: --dev "0002:1e:00.0,gw_mode=1" Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- doc/guides/eventdevs/cnxk.rst | 18 ++++++++++++++++++ drivers/event/cnxk/cn10k_eventdev.c | 3 ++- drivers/event/cnxk/cn9k_eventdev.c | 3 ++- drivers/event/cnxk/cnxk_eventdev.c | 6 ++++++ drivers/event/cnxk/cnxk_eventdev.h | 6 ++++-- 5 files changed, 32 insertions(+), 4 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index cf2156333..b2684d431 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -55,6 +55,24 @@ Runtime Config Options -a 0002:0e:00.0,xae_cnt=16384 +- ``CN9K Getwork mode`` + + CN9K ``single_ws`` devargs parameter is introduced to select single workslot + mode in SSO and disable the default dual workslot mode. + + For example:: + + -a 0002:0e:00.0,single_ws=1 + +- ``CN10K Getwork mode`` + + CN10K supports multiple getwork prefetch modes, by default the prefetch + mode is set to none. + + For example:: + + -a 0002:0e:00.0,gw_mode=1 + - ``Event Group QoS support`` SSO GGRPs i.e. queue uses DRAM & SRAM buffers to hold in-flight diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 3cf07734b..310acc011 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -327,4 +327,5 @@ RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" - CNXK_SSO_GGRP_QOS "="); + CNXK_SSO_GGRP_QOS "=" + CN10K_SSO_GW_MODE "="); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 5be2776cc..44c7a0c3a 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -395,4 +395,5 @@ RTE_PMD_REGISTER_PCI(event_cn9k, cn9k_pci_sso); RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" - CNXK_SSO_GGRP_QOS "="); + CNXK_SSO_GGRP_QOS "=" + CN9K_SSO_SINGLE_WS "=1"); diff --git a/drivers/event/cnxk/cnxk_eventdev.c b/drivers/event/cnxk/cnxk_eventdev.c index 5f4075a31..0e2cc3681 100644 --- a/drivers/event/cnxk/cnxk_eventdev.c +++ b/drivers/event/cnxk/cnxk_eventdev.c @@ -406,6 +406,7 @@ static void cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) { struct rte_kvargs *kvlist; + uint8_t single_ws = 0; if (devargs == NULL) return; @@ -417,6 +418,11 @@ cnxk_sso_parse_devargs(struct cnxk_sso_evdev *dev, struct rte_devargs *devargs) &dev->xae_cnt); rte_kvargs_process(kvlist, CNXK_SSO_GGRP_QOS, &parse_sso_kvargs_dict, dev); + rte_kvargs_process(kvlist, CN9K_SSO_SINGLE_WS, &parse_kvargs_value, + &single_ws); + rte_kvargs_process(kvlist, CN10K_SSO_GW_MODE, &parse_kvargs_value, + &dev->gw_mode); + dev->dual_ws = !single_ws; rte_kvargs_free(kvlist); } diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index bf2c961aa..85f6058f2 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -14,8 +14,10 @@ #include "roc_api.h" -#define CNXK_SSO_XAE_CNT "xae_cnt" -#define CNXK_SSO_GGRP_QOS "qos" +#define CNXK_SSO_XAE_CNT "xae_cnt" +#define CNXK_SSO_GGRP_QOS "qos" +#define CN9K_SSO_SINGLE_WS "single_ws" +#define CN10K_SSO_GW_MODE "gw_mode" #define NSEC2USEC(__ns) ((__ns) / 1E3) #define USEC2NSEC(__us) ((__us)*1E3)