From patchwork Sat Mar 6 16:29:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 88664 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B2DDBA0548; Sat, 6 Mar 2021 17:34:03 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0EAC522A4D0; Sat, 6 Mar 2021 17:31:26 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 19F2A22A4D0 for ; Sat, 6 Mar 2021 17:31:23 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 126GPXiF025580 for ; Sat, 6 Mar 2021 08:31:23 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=jRK+gKjQrO7IrqdVyXxBX92+omFapcgQkBE20pOtDe0=; b=ONXD2IJgBq2bvYFJIO1E/toXcyyKdqKuvCEhekJbd6qPeOiQuYqu4cMmPeSQbmrHHPSy pAGYgRv9QaKRzcwlf0PhBQcQIZabLAKcSFFDKdyebqWFH8pH/AY7a+sC+ZXTg3BkHDP7 N1K0hnhBGx6F0hM2nsA+YNHiUD9sa/39UF41OeFJytjdlxX6jpVZzjPpeild7wCABDZq nnnw/xGxIN4G/7P2uciWl/Xrxn+kSlZBKBuM/pHk27Uzdx/8A2nBOars8XOt2LWW3hRx SVsNY4iMKJkcLj/C90Ti1fvjrrgNT+hbO24Nu0ddWlCZE1K2/f9T16H42zvx1xShtdad nA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 3747yurext-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 06 Mar 2021 08:31:23 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Mar 2021 08:31:21 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 6 Mar 2021 08:31:21 -0800 Received: from BG-LT7430.marvell.com (unknown [10.193.68.121]) by maili.marvell.com (Postfix) with ESMTP id E11283F7040; Sat, 6 Mar 2021 08:31:19 -0800 (PST) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: , Date: Sat, 6 Mar 2021 21:59:27 +0530 Message-ID: <20210306162942.6845-23-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210306162942.6845-1-pbhagavatula@marvell.com> References: <20210306162942.6845-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-06_08:2021-03-03, 2021-03-06 signatures=0 Subject: [dpdk-dev] [PATCH 22/36] event/cnxk: add devargs to disable NPA X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh If the chunks are allocated from NPA then TIM can automatically free them when traversing the list of chunks. Add devargs to disable NPA and use software mempool to manage chunks. Example: --dev "0002:0e:00.0,tim_disable_npa=1" Signed-off-by: Shijith Thotton Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/cnxk.rst | 10 ++++ drivers/event/cnxk/cn10k_eventdev.c | 3 +- drivers/event/cnxk/cn9k_eventdev.c | 3 +- drivers/event/cnxk/cnxk_eventdev.h | 9 +++ drivers/event/cnxk/cnxk_tim_evdev.c | 86 +++++++++++++++++++++-------- drivers/event/cnxk/cnxk_tim_evdev.h | 5 ++ 6 files changed, 92 insertions(+), 24 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index 662df2971..9e14f99f2 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -93,6 +93,16 @@ Runtime Config Options -a 0002:0e:00.0,qos=[1-50-50-50] +- ``TIM disable NPA`` + + By default chunks are allocated from NPA then TIM can automatically free + them when traversing the list of chunks. The ``tim_disable_npa`` devargs + parameter disables NPA and uses software mempool to manage chunks + + For example:: + + -a 0002:0e:00.0,tim_disable_npa=1 + Debugging Options ----------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index 30ca0d901..807e666d3 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -502,4 +502,5 @@ RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" - CN10K_SSO_GW_MODE "="); + CN10K_SSO_GW_MODE "=" + CNXK_TIM_DISABLE_NPA "=1"); diff --git a/drivers/event/cnxk/cn9k_eventdev.c b/drivers/event/cnxk/cn9k_eventdev.c index 773152e55..3e27fce4a 100644 --- a/drivers/event/cnxk/cn9k_eventdev.c +++ b/drivers/event/cnxk/cn9k_eventdev.c @@ -571,4 +571,5 @@ RTE_PMD_REGISTER_PCI_TABLE(event_cn9k, cn9k_pci_sso_map); RTE_PMD_REGISTER_KMOD_DEP(event_cn9k, "vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(event_cn9k, CNXK_SSO_XAE_CNT "=" CNXK_SSO_GGRP_QOS "=" - CN9K_SSO_SINGLE_WS "=1"); + CN9K_SSO_SINGLE_WS "=1" + CNXK_TIM_DISABLE_NPA "=1"); diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index e4051a64b..487c7f822 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -159,6 +159,15 @@ struct cnxk_sso_hws_cookie { bool configured; } __rte_cache_aligned; +static inline int +parse_kvargs_flag(const char *key, const char *value, void *opaque) +{ + RTE_SET_USED(key); + + *(uint8_t *)opaque = !!atoi(value); + return 0; +} + static inline int parse_kvargs_value(const char *key, const char *value, void *opaque) { diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c index 986ad8493..44bcad94d 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.c +++ b/drivers/event/cnxk/cnxk_tim_evdev.c @@ -31,30 +31,43 @@ cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring, cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE; cache_sz = cache_sz != 0 ? cache_sz : 2; tim_ring->nb_chunks += (cache_sz * rte_lcore_count()); - tim_ring->chunk_pool = rte_mempool_create_empty( - pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, cache_sz, 0, - rte_socket_id(), mp_flags); - - if (tim_ring->chunk_pool == NULL) { - plt_err("Unable to create chunkpool."); - return -ENOMEM; - } + if (!tim_ring->disable_npa) { + tim_ring->chunk_pool = rte_mempool_create_empty( + pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, + cache_sz, 0, rte_socket_id(), mp_flags); + + if (tim_ring->chunk_pool == NULL) { + plt_err("Unable to create chunkpool."); + return -ENOMEM; + } - rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool, - rte_mbuf_platform_mempool_ops(), NULL); - if (rc < 0) { - plt_err("Unable to set chunkpool ops"); - goto free; - } + rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool, + rte_mbuf_platform_mempool_ops(), + NULL); + if (rc < 0) { + plt_err("Unable to set chunkpool ops"); + goto free; + } - rc = rte_mempool_populate_default(tim_ring->chunk_pool); - if (rc < 0) { - plt_err("Unable to set populate chunkpool."); - goto free; + rc = rte_mempool_populate_default(tim_ring->chunk_pool); + if (rc < 0) { + plt_err("Unable to set populate chunkpool."); + goto free; + } + tim_ring->aura = roc_npa_aura_handle_to_aura( + tim_ring->chunk_pool->pool_id); + tim_ring->ena_dfb = 0; + } else { + tim_ring->chunk_pool = rte_mempool_create( + pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, + cache_sz, 0, NULL, NULL, NULL, NULL, rte_socket_id(), + mp_flags); + if (tim_ring->chunk_pool == NULL) { + plt_err("Unable to create chunkpool."); + return -ENOMEM; + } + tim_ring->ena_dfb = 1; } - tim_ring->aura = - roc_npa_aura_handle_to_aura(tim_ring->chunk_pool->pool_id); - tim_ring->ena_dfb = 0; return 0; @@ -110,8 +123,17 @@ cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr) tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec); tim_ring->nb_timers = rcfg->nb_timers; tim_ring->chunk_sz = dev->chunk_sz; + tim_ring->disable_npa = dev->disable_npa; + + if (tim_ring->disable_npa) { + tim_ring->nb_chunks = + tim_ring->nb_timers / + CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); + tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts; + } else { + tim_ring->nb_chunks = tim_ring->nb_timers; + } - tim_ring->nb_chunks = tim_ring->nb_timers; tim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz); /* Create buckets. */ tim_ring->bkt = @@ -199,6 +221,24 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags, return 0; } +static void +cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev) +{ + struct rte_kvargs *kvlist; + + if (devargs == NULL) + return; + + kvlist = rte_kvargs_parse(devargs->args, NULL); + if (kvlist == NULL) + return; + + rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag, + &dev->disable_npa); + + rte_kvargs_free(kvlist); +} + void cnxk_tim_init(struct roc_sso *sso) { @@ -217,6 +257,8 @@ cnxk_tim_init(struct roc_sso *sso) } dev = mz->addr; + cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev); + dev->tim.roc_sso = sso; rc = roc_tim_init(&dev->tim); if (rc < 0) { diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 62bb2f1eb..8c21ab1fe 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -33,11 +33,15 @@ #define CN9K_TIM_MIN_TMO_TKS (256) +#define CNXK_TIM_DISABLE_NPA "tim_disable_npa" + struct cnxk_tim_evdev { struct roc_tim tim; struct rte_eventdev *event_dev; uint16_t nb_rings; uint32_t chunk_sz; + /* Dev args */ + uint8_t disable_npa; }; enum cnxk_tim_clk_src { @@ -75,6 +79,7 @@ struct cnxk_tim_ring { struct rte_mempool *chunk_pool; uint64_t arm_cnt; uint8_t prod_type_sp; + uint8_t disable_npa; uint8_t ena_dfb; uint16_t ring_id; uint32_t aura;