From patchwork Sat Mar 6 16:29:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 88668 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B4B8BA0548; Sat, 6 Mar 2021 17:34:44 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A870522A4B6; Sat, 6 Mar 2021 17:31:38 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 70FD522A4B6 for ; Sat, 6 Mar 2021 17:31:36 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 126GQxUu009883 for ; Sat, 6 Mar 2021 08:31:35 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=3Sh4k0RLMX/SQECjeT95rmpcJ4P/RR0JorL7N0/8QzU=; b=FvOhAV/HZgSrHIHSu59MsgqkVqPpP1Wg5JPCFAbKwObnHBr0215bSzcHETR1sgTHiFgk R8gkI8b1FFxT//KLhSwwKrV8TFnGVVHU0w6gM4rBCQ9p1xT1BRGEStIKY2E2iG4TCy4x 6X/cZF5wHokCtDoQOG6D+lH5CtxOGerR8EgrRQhQWZud8IcbpdYSWJe1jVGmcCb51hJd rdqJ9F+ivQfzw3UfL43qSkGuVx12h3xgJvSnYXXc1PPHThuovjNhjnijtrsXwkHmp5Wp W3mcrH78zFFfDW3lTFGNmwQp+p2/WJVqwXL1ot2LDYZMJ6cLj493+H2hvv7YmX5WQDT8 Eg== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 374a4w08r7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 06 Mar 2021 08:31:35 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Mar 2021 08:31:33 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 6 Mar 2021 08:31:33 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 6 Mar 2021 08:31:33 -0800 Received: from BG-LT7430.marvell.com (unknown [10.193.68.121]) by maili.marvell.com (Postfix) with ESMTP id 876603F703F; Sat, 6 Mar 2021 08:31:31 -0800 (PST) From: To: , Pavan Nikhilesh , "Shijith Thotton" CC: , Date: Sat, 6 Mar 2021 21:59:31 +0530 Message-ID: <20210306162942.6845-27-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210306162942.6845-1-pbhagavatula@marvell.com> References: <20210306162942.6845-1-pbhagavatula@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-06_08:2021-03-03, 2021-03-06 signatures=0 Subject: [dpdk-dev] [PATCH 26/36] event/cnxk: add TIM bucket operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add TIM bucket operations used for event timer arm and cancel. Signed-off-by: Pavan Nikhilesh Signed-off-by: Shijith Thotton --- drivers/event/cnxk/cnxk_tim_evdev.h | 30 +++++++ drivers/event/cnxk/cnxk_tim_worker.c | 6 ++ drivers/event/cnxk/cnxk_tim_worker.h | 123 +++++++++++++++++++++++++++ drivers/event/cnxk/meson.build | 1 + 4 files changed, 160 insertions(+) create mode 100644 drivers/event/cnxk/cnxk_tim_worker.c create mode 100644 drivers/event/cnxk/cnxk_tim_worker.h diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h index 6208c150a..c844d9b61 100644 --- a/drivers/event/cnxk/cnxk_tim_evdev.h +++ b/drivers/event/cnxk/cnxk_tim_evdev.h @@ -37,6 +37,36 @@ #define CNXK_TIM_CHNK_SLOTS "tim_chnk_slots" #define CNXK_TIM_RINGS_LMT "tim_rings_lmt" +#define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48) +#define TIM_BUCKET_W1_M_CHUNK_REMAINDER \ + ((1ULL << (64 - TIM_BUCKET_W1_S_CHUNK_REMAINDER)) - 1) +#define TIM_BUCKET_W1_S_LOCK (40) +#define TIM_BUCKET_W1_M_LOCK \ + ((1ULL << (TIM_BUCKET_W1_S_CHUNK_REMAINDER - TIM_BUCKET_W1_S_LOCK)) - 1) +#define TIM_BUCKET_W1_S_RSVD (35) +#define TIM_BUCKET_W1_S_BSK (34) +#define TIM_BUCKET_W1_M_BSK \ + ((1ULL << (TIM_BUCKET_W1_S_RSVD - TIM_BUCKET_W1_S_BSK)) - 1) +#define TIM_BUCKET_W1_S_HBT (33) +#define TIM_BUCKET_W1_M_HBT \ + ((1ULL << (TIM_BUCKET_W1_S_BSK - TIM_BUCKET_W1_S_HBT)) - 1) +#define TIM_BUCKET_W1_S_SBT (32) +#define TIM_BUCKET_W1_M_SBT \ + ((1ULL << (TIM_BUCKET_W1_S_HBT - TIM_BUCKET_W1_S_SBT)) - 1) +#define TIM_BUCKET_W1_S_NUM_ENTRIES (0) +#define TIM_BUCKET_W1_M_NUM_ENTRIES \ + ((1ULL << (TIM_BUCKET_W1_S_SBT - TIM_BUCKET_W1_S_NUM_ENTRIES)) - 1) + +#define TIM_BUCKET_SEMA (TIM_BUCKET_CHUNK_REMAIN) + +#define TIM_BUCKET_CHUNK_REMAIN \ + (TIM_BUCKET_W1_M_CHUNK_REMAINDER << TIM_BUCKET_W1_S_CHUNK_REMAINDER) + +#define TIM_BUCKET_LOCK (TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK) + +#define TIM_BUCKET_SEMA_WLOCK \ + (TIM_BUCKET_CHUNK_REMAIN | (1ull << TIM_BUCKET_W1_S_LOCK)) + struct cnxk_tim_evdev { struct roc_tim tim; struct rte_eventdev *event_dev; diff --git a/drivers/event/cnxk/cnxk_tim_worker.c b/drivers/event/cnxk/cnxk_tim_worker.c new file mode 100644 index 000000000..564687d9b --- /dev/null +++ b/drivers/event/cnxk/cnxk_tim_worker.c @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#include "cnxk_tim_evdev.h" +#include "cnxk_tim_worker.h" diff --git a/drivers/event/cnxk/cnxk_tim_worker.h b/drivers/event/cnxk/cnxk_tim_worker.h new file mode 100644 index 000000000..bd205e5c1 --- /dev/null +++ b/drivers/event/cnxk/cnxk_tim_worker.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#ifndef __CNXK_TIM_WORKER_H__ +#define __CNXK_TIM_WORKER_H__ + +#include "cnxk_tim_evdev.h" + +static inline uint8_t +cnxk_tim_bkt_fetch_lock(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_LOCK) & TIM_BUCKET_W1_M_LOCK; +} + +static inline int16_t +cnxk_tim_bkt_fetch_rem(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_CHUNK_REMAINDER) & + TIM_BUCKET_W1_M_CHUNK_REMAINDER; +} + +static inline int16_t +cnxk_tim_bkt_get_rem(struct cnxk_tim_bkt *bktp) +{ + return __atomic_load_n(&bktp->chunk_remainder, __ATOMIC_ACQUIRE); +} + +static inline void +cnxk_tim_bkt_set_rem(struct cnxk_tim_bkt *bktp, uint16_t v) +{ + __atomic_store_n(&bktp->chunk_remainder, v, __ATOMIC_RELAXED); +} + +static inline void +cnxk_tim_bkt_sub_rem(struct cnxk_tim_bkt *bktp, uint16_t v) +{ + __atomic_fetch_sub(&bktp->chunk_remainder, v, __ATOMIC_RELAXED); +} + +static inline uint8_t +cnxk_tim_bkt_get_hbt(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_HBT) & TIM_BUCKET_W1_M_HBT; +} + +static inline uint8_t +cnxk_tim_bkt_get_bsk(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_BSK) & TIM_BUCKET_W1_M_BSK; +} + +static inline uint64_t +cnxk_tim_bkt_clr_bsk(struct cnxk_tim_bkt *bktp) +{ + /* Clear everything except lock. */ + const uint64_t v = TIM_BUCKET_W1_M_LOCK << TIM_BUCKET_W1_S_LOCK; + + return __atomic_fetch_and(&bktp->w1, v, __ATOMIC_ACQ_REL); +} + +static inline uint64_t +cnxk_tim_bkt_fetch_sema_lock(struct cnxk_tim_bkt *bktp) +{ + return __atomic_fetch_add(&bktp->w1, TIM_BUCKET_SEMA_WLOCK, + __ATOMIC_ACQUIRE); +} + +static inline uint64_t +cnxk_tim_bkt_fetch_sema(struct cnxk_tim_bkt *bktp) +{ + return __atomic_fetch_add(&bktp->w1, TIM_BUCKET_SEMA, __ATOMIC_RELAXED); +} + +static inline uint64_t +cnxk_tim_bkt_inc_lock(struct cnxk_tim_bkt *bktp) +{ + const uint64_t v = 1ull << TIM_BUCKET_W1_S_LOCK; + + return __atomic_fetch_add(&bktp->w1, v, __ATOMIC_ACQUIRE); +} + +static inline void +cnxk_tim_bkt_dec_lock(struct cnxk_tim_bkt *bktp) +{ + __atomic_fetch_sub(&bktp->lock, 1, __ATOMIC_RELEASE); +} + +static inline void +cnxk_tim_bkt_dec_lock_relaxed(struct cnxk_tim_bkt *bktp) +{ + __atomic_fetch_sub(&bktp->lock, 1, __ATOMIC_RELAXED); +} + +static inline uint32_t +cnxk_tim_bkt_get_nent(uint64_t w1) +{ + return (w1 >> TIM_BUCKET_W1_S_NUM_ENTRIES) & + TIM_BUCKET_W1_M_NUM_ENTRIES; +} + +static inline void +cnxk_tim_bkt_inc_nent(struct cnxk_tim_bkt *bktp) +{ + __atomic_add_fetch(&bktp->nb_entry, 1, __ATOMIC_RELAXED); +} + +static inline void +cnxk_tim_bkt_add_nent(struct cnxk_tim_bkt *bktp, uint32_t v) +{ + __atomic_add_fetch(&bktp->nb_entry, v, __ATOMIC_RELAXED); +} + +static inline uint64_t +cnxk_tim_bkt_clr_nent(struct cnxk_tim_bkt *bktp) +{ + const uint64_t v = + ~(TIM_BUCKET_W1_M_NUM_ENTRIES << TIM_BUCKET_W1_S_NUM_ENTRIES); + + return __atomic_and_fetch(&bktp->w1, v, __ATOMIC_ACQ_REL); +} + +#endif /* __CNXK_TIM_WORKER_H__ */ diff --git a/drivers/event/cnxk/meson.build b/drivers/event/cnxk/meson.build index a9566cb09..b40e39397 100644 --- a/drivers/event/cnxk/meson.build +++ b/drivers/event/cnxk/meson.build @@ -15,6 +15,7 @@ sources = files('cn10k_worker.c', 'cnxk_eventdev_adptr.c', 'cnxk_eventdev.c', 'cnxk_sso_selftest.c', + 'cnxk_tim_worker.c', 'cnxk_tim_evdev.c') deps += ['bus_pci', 'common_cnxk', 'net_cnxk']