From patchwork Thu Apr 8 09:50:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ashwin Sekhar T K X-Patchwork-Id: 90866 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D4E28A0579; Thu, 8 Apr 2021 11:51:40 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A7BA5141044; Thu, 8 Apr 2021 11:51:20 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 82367141058 for ; Thu, 8 Apr 2021 11:51:19 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 1389pJBl020773 for ; Thu, 8 Apr 2021 02:51:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=mj8J/pQ7kUa3fsAvqWMQnyHPacc5py+6X7c4uteKjLQ=; b=b5xtSVTvD8gXKPG54ETrap85UXqS/tvSwGxnv98i+x5xp3CkMuTU2JX1x1SJg2fSwFwW pUMvbnW9URt2cGy6Q/Z2AI8ebZmlwkgeBHK9WaknHUR1JVdYXFn0EcaAP6xOFPhePc7r 6pct0aVy30eV4tOy7IVM9GVkl7ll02HzT/pZiHYCdNoDTrcLY6c19BbPVZreMHMtdO85 Sl1wfeSael39t5RqLQxM1QyvhUvFaiHIuchQAZQ9MwC6QAOvG1iY2wce4X5aRn+NNYdf BVXVa5JzyFyXnO8CpdRWUHhp44eruUmufpj0keaHA7EhUCd+wjNX8VIjZTELVFVzyGwp OQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 37swewgf9x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 08 Apr 2021 02:51:18 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Apr 2021 02:51:16 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 8 Apr 2021 02:51:16 -0700 Received: from lab-ci-142.marvell.com (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id A44F83F703F; Thu, 8 Apr 2021 02:51:13 -0700 (PDT) From: Ashwin Sekhar T K To: CC: , , , , , , Date: Thu, 8 Apr 2021 15:20:44 +0530 Message-ID: <20210408095049.3100322-7-asekhar@marvell.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210408095049.3100322-1-asekhar@marvell.com> References: <20210305162149.2196166-1-asekhar@marvell.com> <20210408095049.3100322-1-asekhar@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: _fFYYNrxjQ2f5DzDBTWoTNMXOcdtTBP8 X-Proofpoint-GUID: _fFYYNrxjQ2f5DzDBTWoTNMXOcdtTBP8 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-04-08_02:2021-04-08, 2021-04-08 signatures=0 Subject: [dpdk-dev] [PATCH v4 06/11] mempool/cnxk: add cn9k optimized mempool enqueue/dequeue X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add Marvell CN9k mempool enqueue/dequeue. Marvell CN9k supports burst dequeue which allows to dequeue up to 32 pointers using pipelined casp instructions. Signed-off-by: Pavan Nikhilesh Signed-off-by: Ashwin Sekhar T K --- doc/guides/mempool/cnxk.rst | 4 +++ drivers/mempool/cnxk/cn9k_mempool_ops.c | 39 +++++++++++++++++++++++-- 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/doc/guides/mempool/cnxk.rst b/doc/guides/mempool/cnxk.rst index 907c19c841..f51532b101 100644 --- a/doc/guides/mempool/cnxk.rst +++ b/doc/guides/mempool/cnxk.rst @@ -21,6 +21,10 @@ CNXK NPA PMD supports: - Ethdev Rx buffer allocation in HW to save CPU cycles in the Rx path. - Ethdev Tx buffer recycling in HW to save CPU cycles in the Tx path. +CN9k NPA supports: + +- Burst alloc of up to 32 pointers. + Prerequisites and Compilation procedure --------------------------------------- diff --git a/drivers/mempool/cnxk/cn9k_mempool_ops.c b/drivers/mempool/cnxk/cn9k_mempool_ops.c index f5ac163af9..c0cdba640b 100644 --- a/drivers/mempool/cnxk/cn9k_mempool_ops.c +++ b/drivers/mempool/cnxk/cn9k_mempool_ops.c @@ -7,6 +7,41 @@ #include "roc_api.h" #include "cnxk_mempool.h" +static int __rte_hot +cn9k_mempool_enq(struct rte_mempool *mp, void *const *obj_table, unsigned int n) +{ + /* Ensure mbuf init changes are written before the free pointers + * are enqueued to the stack. + */ + rte_io_wmb(); + roc_npa_aura_op_bulk_free(mp->pool_id, (const uint64_t *)obj_table, n, + 0); + + return 0; +} + +static inline int __rte_hot +cn9k_mempool_deq(struct rte_mempool *mp, void **obj_table, unsigned int n) +{ + unsigned int count; + + count = roc_npa_aura_op_bulk_alloc(mp->pool_id, (uint64_t *)obj_table, + n, 0, 1); + + if (unlikely(count != n)) { + /* If bulk alloc failed to allocate all pointers, try + * allocating remaining pointers with the default alloc + * with retry scheme. + */ + if (cnxk_mempool_deq(mp, &obj_table[count], n - count)) { + cn9k_mempool_enq(mp, obj_table, count); + return -ENOENT; + } + } + + return 0; +} + static int cn9k_mempool_alloc(struct rte_mempool *mp) { @@ -44,8 +79,8 @@ static struct rte_mempool_ops cn9k_mempool_ops = { .name = "cn9k_mempool_ops", .alloc = cn9k_mempool_alloc, .free = cnxk_mempool_free, - .enqueue = cnxk_mempool_enq, - .dequeue = cnxk_mempool_deq, + .enqueue = cn9k_mempool_enq, + .dequeue = cn9k_mempool_deq, .get_count = cnxk_mempool_get_count, .calc_mem_size = cnxk_mempool_calc_mem_size, .populate = cnxk_mempool_populate,