diff --git a/drivers/event/cnxk/cnxk_tim_evdev.c b/drivers/event/cnxk/cnxk_tim_evdev.c
index 6000b507a..986ad8493 100644
--- a/drivers/event/cnxk/cnxk_tim_evdev.c
+++ b/drivers/event/cnxk/cnxk_tim_evdev.c
@@ -5,6 +5,177 @@
 #include "cnxk_eventdev.h"
 #include "cnxk_tim_evdev.h"
 
+static struct rte_event_timer_adapter_ops cnxk_tim_ops;
+
+static int
+cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,
+			  struct rte_event_timer_adapter_conf *rcfg)
+{
+	unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
+	unsigned int mp_flags = 0;
+	char pool_name[25];
+	int rc;
+
+	cache_sz /= rte_lcore_count();
+	/* Create chunk pool. */
+	if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
+		mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
+		plt_tim_dbg("Using single producer mode");
+		tim_ring->prod_type_sp = true;
+	}
+
+	snprintf(pool_name, sizeof(pool_name), "cnxk_tim_chunk_pool%d",
+		 tim_ring->ring_id);
+
+	if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
+		cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
+	cache_sz = cache_sz != 0 ? cache_sz : 2;
+	tim_ring->nb_chunks += (cache_sz * rte_lcore_count());
+	tim_ring->chunk_pool = rte_mempool_create_empty(
+		pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz, cache_sz, 0,
+		rte_socket_id(), mp_flags);
+
+	if (tim_ring->chunk_pool == NULL) {
+		plt_err("Unable to create chunkpool.");
+		return -ENOMEM;
+	}
+
+	rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
+					rte_mbuf_platform_mempool_ops(), NULL);
+	if (rc < 0) {
+		plt_err("Unable to set chunkpool ops");
+		goto free;
+	}
+
+	rc = rte_mempool_populate_default(tim_ring->chunk_pool);
+	if (rc < 0) {
+		plt_err("Unable to set populate chunkpool.");
+		goto free;
+	}
+	tim_ring->aura =
+		roc_npa_aura_handle_to_aura(tim_ring->chunk_pool->pool_id);
+	tim_ring->ena_dfb = 0;
+
+	return 0;
+
+free:
+	rte_mempool_free(tim_ring->chunk_pool);
+	return rc;
+}
+
+static int
+cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
+{
+	struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
+	struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
+	struct cnxk_tim_ring *tim_ring;
+	int rc;
+
+	if (dev == NULL)
+		return -ENODEV;
+
+	if (adptr->data->id >= dev->nb_rings)
+		return -ENODEV;
+
+	tim_ring = rte_zmalloc("cnxk_tim_prv", sizeof(struct cnxk_tim_ring), 0);
+	if (tim_ring == NULL)
+		return -ENOMEM;
+
+	rc = roc_tim_lf_alloc(&dev->tim, adptr->data->id, NULL);
+	if (rc < 0) {
+		plt_err("Failed to create timer ring");
+		goto tim_ring_free;
+	}
+
+	if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(
+			      rcfg->timer_tick_ns,
+			      cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())),
+		      cnxk_tim_cntfrq()) <
+	    cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) {
+		if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
+			rcfg->timer_tick_ns = TICK2NSEC(
+				cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()),
+				cnxk_tim_cntfrq());
+		else {
+			rc = -ERANGE;
+			goto tim_hw_free;
+		}
+	}
+	tim_ring->ring_id = adptr->data->id;
+	tim_ring->clk_src = (int)rcfg->clk_src;
+	tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(
+		rcfg->timer_tick_ns,
+		cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq()));
+	tim_ring->max_tout = rcfg->max_tmo_ns;
+	tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
+	tim_ring->nb_timers = rcfg->nb_timers;
+	tim_ring->chunk_sz = dev->chunk_sz;
+
+	tim_ring->nb_chunks = tim_ring->nb_timers;
+	tim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
+	/* Create buckets. */
+	tim_ring->bkt =
+		rte_zmalloc("cnxk_tim_bucket",
+			    (tim_ring->nb_bkts) * sizeof(struct cnxk_tim_bkt),
+			    RTE_CACHE_LINE_SIZE);
+	if (tim_ring->bkt == NULL)
+		goto tim_hw_free;
+
+	rc = cnxk_tim_chnk_pool_create(tim_ring, rcfg);
+	if (rc < 0)
+		goto tim_bkt_free;
+
+	rc = roc_tim_lf_config(
+		&dev->tim, tim_ring->ring_id,
+		cnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0,
+		tim_ring->nb_bkts, tim_ring->chunk_sz,
+		NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()));
+	if (rc < 0) {
+		plt_err("Failed to configure timer ring");
+		goto tim_chnk_free;
+	}
+
+	tim_ring->base = roc_tim_lf_base_get(&dev->tim, tim_ring->ring_id);
+	plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);
+	plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
+
+	plt_tim_dbg(
+		"Total memory used %" PRIu64 "MB\n",
+		(uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) +
+			    (tim_ring->nb_bkts * sizeof(struct cnxk_tim_bkt))) /
+			   BIT_ULL(20)));
+
+	adptr->data->adapter_priv = tim_ring;
+	return rc;
+
+tim_chnk_free:
+	rte_mempool_free(tim_ring->chunk_pool);
+tim_bkt_free:
+	rte_free(tim_ring->bkt);
+tim_hw_free:
+	roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
+tim_ring_free:
+	rte_free(tim_ring);
+	return rc;
+}
+
+static int
+cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr)
+{
+	struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
+	struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
+
+	if (dev == NULL)
+		return -ENODEV;
+
+	roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
+	rte_free(tim_ring->bkt);
+	rte_mempool_free(tim_ring->chunk_pool);
+	rte_free(tim_ring);
+
+	return 0;
+}
+
 int
 cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
 		  uint32_t *caps,
@@ -18,6 +189,9 @@ cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
 	if (dev == NULL)
 		return -ENODEV;
 
+	cnxk_tim_ops.init = cnxk_tim_ring_create;
+	cnxk_tim_ops.uninit = cnxk_tim_ring_free;
+
 	/* Store evdev pointer for later use. */
 	dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
 	*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
diff --git a/drivers/event/cnxk/cnxk_tim_evdev.h b/drivers/event/cnxk/cnxk_tim_evdev.h
index 8dcecb281..62bb2f1eb 100644
--- a/drivers/event/cnxk/cnxk_tim_evdev.h
+++ b/drivers/event/cnxk/cnxk_tim_evdev.h
@@ -12,12 +12,26 @@
 
 #include <eventdev_pmd_pci.h>
 #include <rte_event_timer_adapter.h>
+#include <rte_malloc.h>
 #include <rte_memzone.h>
 
 #include "roc_api.h"
 
-#define CNXK_TIM_EVDEV_NAME	   cnxk_tim_eventdev
-#define CNXK_TIM_RING_DEF_CHUNK_SZ (4096)
+#define NSECPERSEC		 1E9
+#define USECPERSEC		 1E6
+#define TICK2NSEC(__tck, __freq) (((__tck)*NSECPERSEC) / (__freq))
+
+#define CNXK_TIM_EVDEV_NAME	    cnxk_tim_eventdev
+#define CNXK_TIM_MAX_BUCKETS	    (0xFFFFF)
+#define CNXK_TIM_RING_DEF_CHUNK_SZ  (4096)
+#define CNXK_TIM_CHUNK_ALIGNMENT    (16)
+#define CNXK_TIM_MAX_BURST	    \
+			(RTE_CACHE_LINE_SIZE / CNXK_TIM_CHUNK_ALIGNMENT)
+#define CNXK_TIM_NB_CHUNK_SLOTS(sz) (((sz) / CNXK_TIM_CHUNK_ALIGNMENT) - 1)
+#define CNXK_TIM_MIN_CHUNK_SLOTS    (0x1)
+#define CNXK_TIM_MAX_CHUNK_SLOTS    (0x1FFE)
+
+#define CN9K_TIM_MIN_TMO_TKS (256)
 
 struct cnxk_tim_evdev {
 	struct roc_tim tim;
@@ -26,6 +40,57 @@ struct cnxk_tim_evdev {
 	uint32_t chunk_sz;
 };
 
+enum cnxk_tim_clk_src {
+	CNXK_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
+	CNXK_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
+	CNXK_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
+	CNXK_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
+};
+
+struct cnxk_tim_bkt {
+	uint64_t first_chunk;
+	union {
+		uint64_t w1;
+		struct {
+			uint32_t nb_entry;
+			uint8_t sbt : 1;
+			uint8_t hbt : 1;
+			uint8_t bsk : 1;
+			uint8_t rsvd : 5;
+			uint8_t lock;
+			int16_t chunk_remainder;
+		};
+	};
+	uint64_t current_chunk;
+	uint64_t pad;
+};
+
+struct cnxk_tim_ring {
+	uintptr_t base;
+	uint16_t nb_chunk_slots;
+	uint32_t nb_bkts;
+	uint64_t tck_int;
+	uint64_t tot_int;
+	struct cnxk_tim_bkt *bkt;
+	struct rte_mempool *chunk_pool;
+	uint64_t arm_cnt;
+	uint8_t prod_type_sp;
+	uint8_t ena_dfb;
+	uint16_t ring_id;
+	uint32_t aura;
+	uint64_t nb_timers;
+	uint64_t tck_nsec;
+	uint64_t max_tout;
+	uint64_t nb_chunks;
+	uint64_t chunk_sz;
+	enum cnxk_tim_clk_src clk_src;
+} __rte_cache_aligned;
+
+struct cnxk_tim_ent {
+	uint64_t w0;
+	uint64_t wqe;
+};
+
 static inline struct cnxk_tim_evdev *
 cnxk_tim_priv_get(void)
 {
@@ -38,6 +103,65 @@ cnxk_tim_priv_get(void)
 	return mz->addr;
 }
 
+static inline uint64_t
+cnxk_tim_min_tmo_ticks(uint64_t freq)
+{
+	if (roc_model_runtime_is_cn9k())
+		return CN9K_TIM_MIN_TMO_TKS;
+	else /* CN10K min tick is of 1us */
+		return freq / USECPERSEC;
+}
+
+static inline uint64_t
+cnxk_tim_min_resolution_ns(uint64_t freq)
+{
+	return NSECPERSEC / freq;
+}
+
+static inline enum roc_tim_clk_src
+cnxk_tim_convert_clk_src(enum cnxk_tim_clk_src clk_src)
+{
+	switch (clk_src) {
+	case RTE_EVENT_TIMER_ADAPTER_CPU_CLK:
+		return roc_model_runtime_is_cn9k() ? ROC_TIM_CLK_SRC_10NS :
+							   ROC_TIM_CLK_SRC_GTI;
+	default:
+		return ROC_TIM_CLK_SRC_INVALID;
+	}
+}
+
+#ifdef RTE_ARCH_ARM64
+static inline uint64_t
+cnxk_tim_cntvct(void)
+{
+	uint64_t tsc;
+
+	asm volatile("mrs %0, cntvct_el0" : "=r"(tsc));
+	return tsc;
+}
+
+static inline uint64_t
+cnxk_tim_cntfrq(void)
+{
+	uint64_t freq;
+
+	asm volatile("mrs %0, cntfrq_el0" : "=r"(freq));
+	return freq;
+}
+#else
+static inline uint64_t
+cnxk_tim_cntvct(void)
+{
+	return 0;
+}
+
+static inline uint64_t
+cnxk_tim_cntfrq(void)
+{
+	return 0;
+}
+#endif
+
 int cnxk_tim_caps_get(const struct rte_eventdev *dev, uint64_t flags,
 		      uint32_t *caps,
 		      const struct rte_event_timer_adapter_ops **ops);
