diff --git a/drivers/net/bnxt/tf_core/tf_core.c b/drivers/net/bnxt/tf_core/tf_core.c
index b1ce4e721c..ebe0fc34aa 100644
--- a/drivers/net/bnxt/tf_core/tf_core.c
+++ b/drivers/net/bnxt/tf_core/tf_core.c
@@ -19,6 +19,7 @@
 #include "rand.h"
 #include "tf_common.h"
 #include "hwrm_tf.h"
+#include "tf_ext_flow_handle.h"
 
 int
 tf_open_session(struct tf *tfp,
@@ -251,6 +252,7 @@ int tf_delete_em_entry(struct tf *tfp,
 	struct tf_session      *tfs;
 	struct tf_dev_info     *dev;
 	int rc;
+	unsigned int flag = 0;
 
 	TF_CHECK_PARMS2(tfp, parms);
 
@@ -274,12 +276,11 @@ int tf_delete_em_entry(struct tf *tfp,
 		return rc;
 	}
 
-	if (parms->mem == TF_MEM_EXTERNAL)
-		rc = dev->ops->tf_dev_delete_ext_em_entry(tfp, parms);
-	else if (parms->mem == TF_MEM_INTERNAL)
+	TF_GET_FLAG_FROM_FLOW_HANDLE(parms->flow_handle, flag);
+	if ((flag & TF_FLAGS_FLOW_HANDLE_INTERNAL))
 		rc = dev->ops->tf_dev_delete_int_em_entry(tfp, parms);
 	else
-		return -EINVAL;
+		rc = dev->ops->tf_dev_delete_ext_em_entry(tfp, parms);
 
 	if (rc) {
 		TFP_DRV_LOG(ERR,
diff --git a/drivers/net/bnxt/tf_core/tf_core.h b/drivers/net/bnxt/tf_core/tf_core.h
index 5e458c58fb..4fe0590569 100644
--- a/drivers/net/bnxt/tf_core/tf_core.h
+++ b/drivers/net/bnxt/tf_core/tf_core.h
@@ -158,34 +158,40 @@ enum tf_device_type {
  */
 enum tf_identifier_type {
 	/**
+	 *  WH/SR/TH/SR2
 	 *  The L2 Context is returned from the L2 Ctxt TCAM lookup
 	 *  and can be used in WC TCAM or EM keys to virtualize further
 	 *  lookups.
 	 */
 	TF_IDENT_TYPE_L2_CTXT_HIGH,
 	/**
+	 *  WH/SR/TH/SR2
 	 *  The L2 Context is returned from the L2 Ctxt TCAM lookup
 	 *  and can be used in WC TCAM or EM keys to virtualize further
 	 *  lookups.
 	 */
 	TF_IDENT_TYPE_L2_CTXT_LOW,
 	/**
+	 *  WH/SR/TH/SR2
 	 *  The WC profile func is returned from the L2 Ctxt TCAM lookup
 	 *  to enable virtualization of the profile TCAM.
 	 */
 	TF_IDENT_TYPE_PROF_FUNC,
 	/**
+	 *  WH/SR/TH/SR2
 	 *  The WC profile ID is included in the WC lookup key
 	 *  to enable virtualization of the WC TCAM hardware.
 	 */
 	TF_IDENT_TYPE_WC_PROF,
 	/**
+	 *  WH/SR/TH/SR2
 	 *  The EM profile ID is included in the EM lookup key
 	 *  to enable virtualization of the EM hardware. (not required for SR2
 	 *  as it has table scope)
 	 */
 	TF_IDENT_TYPE_EM_PROF,
 	/**
+	 *  TH/SR2
 	 *  The L2 func is included in the ILT result and from recycling to
 	 *  enable virtualization of further lookups.
 	 */
@@ -203,59 +209,63 @@ enum tf_identifier_type {
 enum tf_tbl_type {
 	/* Internal */
 
-	/** Wh+/SR Action Record */
+	/** Wh+/SR/TH Action Record */
 	TF_TBL_TYPE_FULL_ACT_RECORD,
-	/** Wh+/SR/Th Multicast Groups */
+	/** TH Compact Action Record */
+	TF_TBL_TYPE_COMPACT_ACT_RECORD,
+	/** (Future) Multicast Groups */
 	TF_TBL_TYPE_MCAST_GROUPS,
-	/** Wh+/SR Action Encap 8 Bytes */
+	/** Wh+/SR/TH Action Encap 8 Bytes */
 	TF_TBL_TYPE_ACT_ENCAP_8B,
-	/** Wh+/SR Action Encap 16 Bytes */
+	/** Wh+/SR/TH Action Encap 16 Bytes */
 	TF_TBL_TYPE_ACT_ENCAP_16B,
-	/** Action Encap 32 Bytes */
+	/** WH+/SR/TH Action Encap 32 Bytes */
 	TF_TBL_TYPE_ACT_ENCAP_32B,
-	/** Wh+/SR Action Encap 64 Bytes */
+	/** Wh+/SR/TH Action Encap 64 Bytes */
 	TF_TBL_TYPE_ACT_ENCAP_64B,
-	/** Action Source Properties SMAC */
+	/** WH+/SR/TH Action Source Properties SMAC */
 	TF_TBL_TYPE_ACT_SP_SMAC,
-	/** Wh+/SR Action Source Properties SMAC IPv4 */
+	/** Wh+/SR/TH Action Source Properties SMAC IPv4 */
 	TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
-	/** Action Source Properties SMAC IPv6 */
+	/** WH+/SR/TH Action Source Properties SMAC IPv6 */
 	TF_TBL_TYPE_ACT_SP_SMAC_IPV6,
-	/** Wh+/SR Action Statistics 64 Bits */
+	/** Wh+/SR/TH Action Statistics 64 Bits */
 	TF_TBL_TYPE_ACT_STATS_64,
-	/** Wh+/SR Action Modify L4 Src Port */
-	TF_TBL_TYPE_ACT_MODIFY_SPORT,
-	/** Wh+/SR Action Modify L4 Dest Port */
-	TF_TBL_TYPE_ACT_MODIFY_DPORT,
 	/** Wh+/SR Action Modify IPv4 Source */
 	TF_TBL_TYPE_ACT_MODIFY_IPV4,
-	/** Meter Profiles */
+	/** TH 8B Modify Record */
+	TF_TBL_TYPE_ACT_MODIFY_8B,
+	/** TH 16B Modify Record */
+	TF_TBL_TYPE_ACT_MODIFY_16B,
+	/** TH 32B Modify Record */
+	TF_TBL_TYPE_ACT_MODIFY_32B,
+	/** TH 64B Modify Record */
+	TF_TBL_TYPE_ACT_MODIFY_64B,
+	/** (Future) Meter Profiles */
 	TF_TBL_TYPE_METER_PROF,
-	/** Meter Instance */
+	/** (Future) Meter Instance */
 	TF_TBL_TYPE_METER_INST,
-	/** Mirror Config */
+	/** Wh+/SR/Th Mirror Config */
 	TF_TBL_TYPE_MIRROR_CONFIG,
-	/** UPAR */
+	/** (Future) UPAR */
 	TF_TBL_TYPE_UPAR,
-	/** SR2 Epoch 0 table */
+	/** (Future) SR2 Epoch 0 table */
 	TF_TBL_TYPE_EPOCH0,
-	/** SR2 Epoch 1 table  */
+	/** (Future) SR2 Epoch 1 table  */
 	TF_TBL_TYPE_EPOCH1,
-	/** SR2 Metadata  */
+	/** (Future) TH/SR2 Metadata  */
 	TF_TBL_TYPE_METADATA,
-	/** SR2 CT State  */
+	/** (Future) TH/SR2 CT State  */
 	TF_TBL_TYPE_CT_STATE,
-	/** SR2 Range Profile  */
+	/** (Future) TH/SR2 Range Profile  */
 	TF_TBL_TYPE_RANGE_PROF,
-	/** SR2 Range Entry  */
+	/** (Future) SR2 Range Entry  */
 	TF_TBL_TYPE_RANGE_ENTRY,
-	/** SR2 LAG Entry  */
+	/** (Future) SR2 LAG Entry  */
 	TF_TBL_TYPE_LAG,
-	/** SR2 VNIC/SVIF Table */
-	TF_TBL_TYPE_VNIC_SVIF,
-	/** Th/SR2 EM Flexible Key builder */
+	/** TH/SR2 EM Flexible Key builder */
 	TF_TBL_TYPE_EM_FKB,
-	/** Th/SR2 WC Flexible Key builder */
+	/** TH/SR2 WC Flexible Key builder */
 	TF_TBL_TYPE_WC_FKB,
 
 	/* External */
@@ -263,9 +273,18 @@ enum tf_tbl_type {
 	/**
 	 * External table type - initially 1 poolsize entries.
 	 * All External table types are associated with a table
-	 * scope. Internal types are not.
+	 * scope. Internal types are not.  Currently this is
+	 * a pool of 64B entries.
 	 */
 	TF_TBL_TYPE_EXT,
+	/* (Future) SR2 32B External EM Action 32B Pool */
+	TF_TBL_TYPE_EXT_32B,
+	/* (Future) SR2 64B External EM Action 64B Pool */
+	TF_TBL_TYPE_EXT_64B,
+	/* (Future) SR2 96B External EM Action 96B Pool */
+	TF_TBL_TYPE_EXT_96B,
+	/* (Future) SR2 128B External EM Action 128B Pool */
+	TF_TBL_TYPE_EXT_128B,
 	TF_TBL_TYPE_MAX
 };
 
@@ -1998,8 +2017,8 @@ enum tf_if_tbl_type {
 	TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR,
 	/** SR2 Ingress lookup table */
 	TF_IF_TBL_TYPE_ILT,
-	/** SR2 VNIC/SVIF Table */
-	TF_IF_TBL_TYPE_VNIC_SVIF,
+	/** SR2 VNIC/SVIF Properties Table */
+	TF_IF_TBL_TYPE_VSPT,
 	TF_IF_TBL_TYPE_MAX
 };
 
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index d4c93439ec..d072b9877c 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -153,11 +153,8 @@ tf_dev_bind_p4(struct tf *tfp,
 	/*
 	 * EEM
 	 */
-	if (dev_handle->type == TF_DEVICE_TYPE_WH)
-		em_cfg.cfg = tf_em_ext_p4;
-	else
-		em_cfg.cfg = tf_em_ext_p45;
 
+	em_cfg.cfg = tf_em_ext_p4;
 	rsv_cnt = tf_dev_reservation_check(tfp,
 					   TF_EM_TBL_TYPE_MAX,
 					   em_cfg.cfg,
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 6b28f6ce59..f6c8f5efd0 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -19,76 +19,41 @@
 #define TF_DEV_P4_PF_MASK 0xfUL
 
 const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {
-	/* CFA_RESOURCE_TYPE_P4_MCG */
-	"mc_group",
-	/* CFA_RESOURCE_TYPE_P4_ENCAP_8B */
-	"encap_8 ",
-	/* CFA_RESOURCE_TYPE_P4_ENCAP_16B */
-	"encap_16",
-	/* CFA_RESOURCE_TYPE_P4_ENCAP_64B */
-	"encap_64",
-	/* CFA_RESOURCE_TYPE_P4_SP_MAC */
-	"sp_mac  ",
-	/* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 */
-	"sp_macv4",
-	/* CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 */
-	"sp_macv6",
-	/* CFA_RESOURCE_TYPE_P4_COUNTER_64B */
-	"ctr_64b ",
-	/* CFA_RESOURCE_TYPE_P4_NAT_PORT */
-	"nat_port",
-	/* CFA_RESOURCE_TYPE_P4_NAT_IPV4 */
-	"nat_ipv4",
-	/* CFA_RESOURCE_TYPE_P4_METER */
-	"meter   ",
-	/* CFA_RESOURCE_TYPE_P4_FLOW_STATE */
-	"flow_st ",
-	/* CFA_RESOURCE_TYPE_P4_FULL_ACTION */
-	"full_act",
-	/* CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION */
-	"fmt0_act",
-	/* CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION */
-	"ext0_act",
-	/* CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION */
-	"fmt1_act",
-	/* CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION */
-	"fmt2_act",
-	/* CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION */
-	"fmt3_act",
-	/* CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION */
-	"fmt4_act",
-	/* CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION */
-	"fmt5_act",
-	/* CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION */
-	"fmt6_act",
-	/* CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH */
-	"l2ctx_hi",
-	/* CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW */
-	"l2ctx_lo",
-	/* CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH */
-	"l2ctr_hi",
-	/* CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW */
-	"l2ctr_lo",
-	/* CFA_RESOURCE_TYPE_P4_PROF_FUNC */
-	"prf_func",
-	/* CFA_RESOURCE_TYPE_P4_PROF_TCAM */
-	"prf_tcam",
-	/* CFA_RESOURCE_TYPE_P4_EM_PROF_ID */
-	"em_prof ",
-	/* CFA_RESOURCE_TYPE_P4_EM_REC */
-	"em_rec  ",
-	/* CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID */
-	"wc_prof ",
-	/* CFA_RESOURCE_TYPE_P4_WC_TCAM */
-	"wc_tcam ",
-	/* CFA_RESOURCE_TYPE_P4_METER_PROF */
-	"mtr_prof",
-	/* CFA_RESOURCE_TYPE_P4_MIRROR */
-	"mirror  ",
-	/* CFA_RESOURCE_TYPE_P4_SP_TCAM */
-	"sp_tcam ",
-	/* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */
-	"tb_scope",
+	[CFA_RESOURCE_TYPE_P4_MCG] = "mc_group",
+	[CFA_RESOURCE_TYPE_P4_ENCAP_8B] = "encap_8 ",
+	[CFA_RESOURCE_TYPE_P4_ENCAP_16B] = "encap_16",
+	[CFA_RESOURCE_TYPE_P4_ENCAP_64B] = "encap_64",
+	[CFA_RESOURCE_TYPE_P4_SP_MAC] =	"sp_mac  ",
+	[CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4] = "sp_macv4",
+	[CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6] = "sp_macv6",
+	[CFA_RESOURCE_TYPE_P4_COUNTER_64B] = "ctr_64b ",
+	[CFA_RESOURCE_TYPE_P4_NAT_PORT] = "nat_port",
+	[CFA_RESOURCE_TYPE_P4_NAT_IPV4] = "nat_ipv4",
+	[CFA_RESOURCE_TYPE_P4_METER] = "meter   ",
+	[CFA_RESOURCE_TYPE_P4_FLOW_STATE] = "flow_st ",
+	[CFA_RESOURCE_TYPE_P4_FULL_ACTION] = "full_act",
+	[CFA_RESOURCE_TYPE_P4_FORMAT_0_ACTION] = "fmt0_act",
+	[CFA_RESOURCE_TYPE_P4_EXT_FORMAT_0_ACTION] = "ext0_act",
+	[CFA_RESOURCE_TYPE_P4_FORMAT_1_ACTION] = "fmt1_act",
+	[CFA_RESOURCE_TYPE_P4_FORMAT_2_ACTION] = "fmt2_act",
+	[CFA_RESOURCE_TYPE_P4_FORMAT_3_ACTION] = "fmt3_act",
+	[CFA_RESOURCE_TYPE_P4_FORMAT_4_ACTION] = "fmt4_act",
+	[CFA_RESOURCE_TYPE_P4_FORMAT_5_ACTION] = "fmt5_act",
+	[CFA_RESOURCE_TYPE_P4_FORMAT_6_ACTION] = "fmt6_act",
+	[CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH] = "l2ctx_hi",
+	[CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW] = "l2ctx_lo",
+	[CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH] = "l2ctr_hi",
+	[CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW] = "l2ctr_lo",
+	[CFA_RESOURCE_TYPE_P4_PROF_FUNC] = "prf_func",
+	[CFA_RESOURCE_TYPE_P4_PROF_TCAM] = "prf_tcam",
+	[CFA_RESOURCE_TYPE_P4_EM_PROF_ID] = "em_prof ",
+	[CFA_RESOURCE_TYPE_P4_EM_REC] = "em_rec  ",
+	[CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID] = "wc_prof ",
+	[CFA_RESOURCE_TYPE_P4_WC_TCAM] = "wc_tcam ",
+	[CFA_RESOURCE_TYPE_P4_METER_PROF] = "mtr_prof",
+	[CFA_RESOURCE_TYPE_P4_MIRROR] = "mirror  ",
+	[CFA_RESOURCE_TYPE_P4_SP_TCAM] = "sp_tcam ",
+	[CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope",
 };
 
 /**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index bfad02a0b8..ee283ce29d 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -13,98 +13,123 @@
 #include "tf_global_cfg.h"
 
 struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID },
-	/* CFA_RESOURCE_TYPE_P4_L2_FUNC */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+	[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH
+	},
+	[TF_IDENT_TYPE_L2_CTXT_LOW] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_LOW
+	},
+	[TF_IDENT_TYPE_PROF_FUNC] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_FUNC
+	},
+	[TF_IDENT_TYPE_WC_PROF] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM_PROF_ID
+	},
+	[TF_IDENT_TYPE_EM_PROF] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_EM_PROF_ID
+	},
 };
 
 struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM },
-	/* CFA_RESOURCE_TYPE_P4_CT_RULE_TCAM */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_VEB_TCAM */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
+	[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_HIGH
+	},
+	[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_TCAM_LOW
+	},
+	[TF_TCAM_TBL_TYPE_PROF_TCAM] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_PROF_TCAM
+	},
+	[TF_TCAM_TBL_TYPE_WC_TCAM] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_WC_TCAM
+	},
+	[TF_TCAM_TBL_TYPE_SP_TCAM] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_TCAM
+	},
 };
 
 struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B },
-	/* CFA_RESOURCE_TYPE_P4_ENCAP_32B */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4 },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6 },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_PORT },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4 },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR },
-	/* CFA_RESOURCE_TYPE_P4_UPAR */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_EPOC */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_METADATA */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_CT_STATE */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_RANGE_PROF */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_RANGE_ENTRY */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_LAG */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_VNIC_SVIF */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_EM_FBK */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_WC_FKB */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P4_EXT */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
-};
+	[TF_TBL_TYPE_FULL_ACT_RECORD] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION
+	},
+	[TF_TBL_TYPE_MCAST_GROUPS] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG
+	},
+	[TF_TBL_TYPE_ACT_ENCAP_8B] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B
+	},
+	[TF_TBL_TYPE_ACT_ENCAP_16B] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B
+	},
+	[TF_TBL_TYPE_ACT_ENCAP_64B] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B
+	},
+	[TF_TBL_TYPE_ACT_SP_SMAC] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC
+	},
+	[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4
+	},
+	[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6
+	},
+	[TF_TBL_TYPE_ACT_STATS_64] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B
+	},
+	[TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4
+	},
+	[TF_TBL_TYPE_METER_PROF] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF
+	},
+	[TF_TBL_TYPE_METER_INST] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER
+	},
+	[TF_TBL_TYPE_MIRROR_CONFIG] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR
+	},
 
-struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
-	/* CFA_RESOURCE_TYPE_P4_EM_REC */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE },
 };
 
-struct tf_rm_element_cfg tf_em_ext_p45[TF_EM_TBL_TYPE_MAX] = {
-	/* CFA_RESOURCE_TYPE_P4_EM_REC */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
+struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
+	[TF_EM_TBL_TYPE_TBL_SCOPE] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE
+	},
 };
 
 struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
-	{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC },
-	/* CFA_RESOURCE_TYPE_P4_TBL_SCOPE */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
+	[TF_EM_TBL_TYPE_EM_RECORD] = {
+		TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P4_EM_REC
+	},
 };
 
+/* Note that hcapi_types from this table are from hcapi_cfa_p4.h
+ * These are not CFA resource types because they are not allocated
+ * CFA resources - they are identifiers for the interface tables
+ * shared between the firmware and the host.  It may make sense to
+ * move these types to cfa_resource_types.h.
+ */
 struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
-	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },
-	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },
-	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },
-	{ TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },
-	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },
-	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }
+	[TF_IF_TBL_TYPE_PROF_SPIF_DFLT_L2_CTXT] = {
+		TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT
+	},
+	[TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR] = {
+		TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR
+	},
+	[TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR] = {
+		TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR
+	},
+	[TF_IF_TBL_TYPE_LKUP_PARIF_DFLT_ACT_REC_PTR] = {
+		TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR
+	},
 };
 
 struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
-	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },
-	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },
+	[TF_TUNNEL_ENCAP] = {
+		TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP
+	},
+	[TF_ACTION_BLOCK] = {
+		TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK
+	},
 };
 #endif /* _TF_DEVICE_P4_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p45.h b/drivers/net/bnxt/tf_core/tf_device_p45.h
deleted file mode 100644
index 13e04c63fc..0000000000
--- a/drivers/net/bnxt/tf_core/tf_device_p45.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2019-2021 Broadcom
- * All rights reserved.
- */
-
-#ifndef _TF_DEVICE_P45_H_
-#define _TF_DEVICE_P45_H_
-
-#include <cfa_resource_types.h>
-
-#include "tf_core.h"
-#include "tf_rm.h"
-#include "tf_if_tbl.h"
-#include "tf_global_cfg.h"
-
-struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_HIGH },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_REMAP_LOW },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_FUNC },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM_PROF_ID },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_EM_PROF_ID },
-	/* CFA_RESOURCE_TYPE_P45_L2_FUNC */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
-};
-
-struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_HIGH },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_L2_CTXT_TCAM_LOW },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_PROF_TCAM },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_WC_TCAM },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_TCAM },
-	/* CFA_RESOURCE_TYPE_P45_CT_RULE_TCAM */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_VEB_TCAM */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
-};
-
-struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_FULL_ACTION },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MCG },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_8B },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_16B },
-	/* CFA_RESOURCE_TYPE_P45_ENCAP_32B */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_ENCAP_64B },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV4 },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_SP_MAC_IPV6 },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_COUNTER_64B },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_PORT },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_NAT_IPV4 },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER_PROF },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_METER },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_MIRROR },
-	/* CFA_RESOURCE_TYPE_P45_UPAR */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_EPOC */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_METADATA */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_CT_STATE */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_RANGE_PROF */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_RANGE_ENTRY */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_LAG */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_VNIC_SVIF */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_EM_FBK */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_WC_FKB */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	/* CFA_RESOURCE_TYPE_P45_EXT */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID }
-};
-
-struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
-	/* CFA_RESOURCE_TYPE_P45_EM_REC */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-	{ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P45_TBL_SCOPE },
-};
-
-struct tf_rm_element_cfg tf_em_int_p4[TF_EM_TBL_TYPE_MAX] = {
-	{ TF_RM_ELEM_CFG_HCAPI, CFA_RESOURCE_TYPE_P45_EM_REC },
-	/* CFA_RESOURCE_TYPE_P45_TBL_SCOPE */
-	{ TF_RM_ELEM_CFG_NULL, CFA_RESOURCE_TYPE_INVALID },
-};
-
-struct tf_if_tbl_cfg tf_if_tbl_p4[TF_IF_TBL_TYPE_MAX] = {
-	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_SPIF_DFLT_L2CTXT },
-	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_DFLT_ACT_REC_PTR },
-	{ TF_IF_TBL_CFG, CFA_P4_TBL_PROF_PARIF_ERR_ACT_REC_PTR },
-	{ TF_IF_TBL_CFG, CFA_P4_TBL_LKUP_PARIF_DFLT_ACT_REC_PTR },
-	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID },
-	{ TF_IF_TBL_CFG_NULL, CFA_IF_TBL_TYPE_INVALID }
-};
-
-struct tf_global_cfg_cfg tf_global_cfg_p4[TF_GLOBAL_CFG_TYPE_MAX] = {
-	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_TUNNEL_ENCAP },
-	{ TF_GLOBAL_CFG_CFG_HCAPI, TF_ACTION_BLOCK },
-};
-#endif /* _TF_DEVICE_P45_H_ */
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.c b/drivers/net/bnxt/tf_core/tf_device_p58.c
index b4530f8762..7dd806000c 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.c
@@ -18,47 +18,28 @@
 #define TF_DEV_P58_PARIF_MAX 16
 #define TF_DEV_P58_PF_MASK 0xfUL
 
+/* For print alignment, make all entries 8 chars in this table */
 const char *tf_resource_str_p58[CFA_RESOURCE_TYPE_P58_LAST + 1] = {
-	/* CFA_RESOURCE_TYPE_P58_METER */
-	"meter   ",
-	/* CFA_RESOURCE_TYPE_P58_SRAM_BANK_0 */
-	"sram_bk0",
-	/* CFA_RESOURCE_TYPE_P58_SRAM_BANK_1 */
-	"sram_bk1",
-	/* CFA_RESOURCE_TYPE_P58_SRAM_BANK_2 */
-	"sram_bk2",
-	/* CFA_RESOURCE_TYPE_P58_SRAM_BANK_3 */
-	"sram_bk3",
-	/* CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH */
-	"l2ctx_hi",
-	/* CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW */
-	"l2ctx_lo",
-	/* CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH */
-	"l2ctr_hi",
-	/* CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW */
-	"l2ctr_lo",
-	/* CFA_RESOURCE_TYPE_P58_PROF_FUNC */
-	"prf_func",
-	/* CFA_RESOURCE_TYPE_P58_PROF_TCAM */
-	"prf_tcam",
-	/* CFA_RESOURCE_TYPE_P58_EM_PROF_ID */
-	"em_prof ",
-	/* CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID */
-	"wc_prof ",
-	/* CFA_RESOURCE_TYPE_P58_EM_REC */
-	"em_rec  ",
-	/* CFA_RESOURCE_TYPE_P58_WC_TCAM */
-	"wc_tcam ",
-	/* CFA_RESOURCE_TYPE_P58_METER_PROF */
-	"mtr_prof",
-	/* CFA_RESOURCE_TYPE_P58_MIRROR */
-	"mirror  ",
-	/* CFA_RESOURCE_TYPE_P58_EM_FKB */
-	"em_fkb  ",
-	/* CFA_RESOURCE_TYPE_P58_WC_FKB */
-	"wc_fkb  ",
-	/* CFA_RESOURCE_TYPE_P58_VEB_TCAM */
-	"veb     ",
+	[CFA_RESOURCE_TYPE_P58_METER]              = "meter   ",
+	[CFA_RESOURCE_TYPE_P58_SRAM_BANK_0]        = "sram_bk0",
+	[CFA_RESOURCE_TYPE_P58_SRAM_BANK_1]        = "sram_bk1",
+	[CFA_RESOURCE_TYPE_P58_SRAM_BANK_2]        = "sram_bk2",
+	[CFA_RESOURCE_TYPE_P58_SRAM_BANK_3]        = "sram_bk3",
+	[CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_HIGH]  = "l2ctx_hi",
+	[CFA_RESOURCE_TYPE_P58_L2_CTXT_TCAM_LOW]   = "l2ctx_lo",
+	[CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_HIGH] = "l2ctr_hi",
+	[CFA_RESOURCE_TYPE_P58_L2_CTXT_REMAP_LOW]  = "l2ctr_lo",
+	[CFA_RESOURCE_TYPE_P58_PROF_FUNC]          = "prf_func",
+	[CFA_RESOURCE_TYPE_P58_PROF_TCAM]          = "prf_tcam",
+	[CFA_RESOURCE_TYPE_P58_EM_PROF_ID]         = "em_prof ",
+	[CFA_RESOURCE_TYPE_P58_WC_TCAM_PROF_ID]    = "wc_prof ",
+	[CFA_RESOURCE_TYPE_P58_EM_REC]             = "em_rec  ",
+	[CFA_RESOURCE_TYPE_P58_WC_TCAM]            = "wc_tcam ",
+	[CFA_RESOURCE_TYPE_P58_METER_PROF]         = "mtr_prof",
+	[CFA_RESOURCE_TYPE_P58_MIRROR]             = "mirror  ",
+	[CFA_RESOURCE_TYPE_P58_EM_FKB]             = "em_fkb  ",
+	[CFA_RESOURCE_TYPE_P58_WC_FKB]             = "wc_fkb  ",
+	[CFA_RESOURCE_TYPE_P58_VEB_TCAM]           = "veb     ",
 };
 
 /**
diff --git a/drivers/net/bnxt/tf_core/tf_device_p58.h b/drivers/net/bnxt/tf_core/tf_device_p58.h
index 3d6e3240bf..de7bb1cd76 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p58.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p58.h
@@ -49,6 +49,12 @@ struct tf_rm_element_cfg tf_tcam_p58[TF_TCAM_TBL_TYPE_MAX] = {
 };
 
 struct tf_rm_element_cfg tf_tbl_p58[TF_TBL_TYPE_MAX] = {
+	[TF_TBL_TYPE_EM_FKB] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_EM_FKB
+	},
+	[TF_TBL_TYPE_WC_FKB] = {
+		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_WC_FKB
+	},
 	[TF_TBL_TYPE_METER_PROF] = {
 		TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P58_METER_PROF
 	},
diff --git a/drivers/net/bnxt/tf_core/tf_em_common.c b/drivers/net/bnxt/tf_core/tf_em_common.c
index ddc6b3c4dd..6cd6086685 100644
--- a/drivers/net/bnxt/tf_core/tf_em_common.c
+++ b/drivers/net/bnxt/tf_core/tf_em_common.c
@@ -777,7 +777,7 @@ tf_insert_eem_entry(struct tf_tbl_scope_cb *tbl_scope_cb,
 	TF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle,
 				     0,
 				     0,
-				     0,
+				     TF_FLAGS_FLOW_HANDLE_EXTERNAL,
 				     index,
 				     0,
 				     table_type);
diff --git a/drivers/net/bnxt/tf_core/tf_em_internal.c b/drivers/net/bnxt/tf_core/tf_em_internal.c
index 62ccd7b78f..bdffd801b3 100644
--- a/drivers/net/bnxt/tf_core/tf_em_internal.c
+++ b/drivers/net/bnxt/tf_core/tf_em_internal.c
@@ -203,7 +203,7 @@ tf_em_insert_int_entry(struct tf *tfp,
 	TF_SET_FIELDS_IN_FLOW_HANDLE(parms->flow_handle,
 				     (uint32_t)num_of_entries,
 				     0,
-				     0,
+				     TF_FLAGS_FLOW_HANDLE_INTERNAL,
 				     rptr_index,
 				     rptr_entry,
 				     0);
diff --git a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
index 9eb5aeb771..bf6dbcd238 100644
--- a/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
+++ b/drivers/net/bnxt/tf_core/tf_ext_flow_handle.h
@@ -19,6 +19,9 @@
 #define TF_HASH_TYPE_FLOW_HANDLE_MASK		0x0000000100000000ULL
 #define TF_HASH_TYPE_FLOW_HANDLE_SFT		32
 
+#define TF_FLAGS_FLOW_HANDLE_INTERNAL		0x2
+#define TF_FLAGS_FLOW_HANDLE_EXTERNAL		0x0
+
 #define TF_FLOW_HANDLE_MASK (TF_NUM_KEY_ENTRIES_FLOW_HANDLE_MASK |	\
 				TF_FLOW_TYPE_FLOW_HANDLE_MASK |		\
 				TF_FLAGS_FLOW_HANDLE_MASK |		\
@@ -92,15 +95,23 @@ do {									\
 
 #define TF_GET_NUM_KEY_ENTRIES_FROM_FLOW_HANDLE(flow_handle,		\
 					  num_key_entries)		\
+do {									\
 	(num_key_entries =						\
 		(((flow_handle) & TF_NUM_KEY_ENTRIES_FLOW_HANDLE_MASK) >> \
-		     TF_NUM_KEY_ENTRIES_FLOW_HANDLE_SFT))		\
+		     TF_NUM_KEY_ENTRIES_FLOW_HANDLE_SFT));		\
+} while (0)
 
 #define TF_GET_ENTRY_NUM_FROM_FLOW_HANDLE(flow_handle,		\
 					  entry_num)		\
+do {									\
 	(entry_num =						\
 		(((flow_handle) & TF_ENTRY_NUM_FLOW_HANDLE_MASK) >> \
-		     TF_ENTRY_NUM_FLOW_HANDLE_SFT))		\
+		     TF_ENTRY_NUM_FLOW_HANDLE_SFT));		\
+} while (0)
+
+#define TF_GET_FLAG_FROM_FLOW_HANDLE(flow_handle, flag)		\
+	(flag =	(((flow_handle) & TF_FLAGS_FLOW_HANDLE_MASK) >>\
+		     TF_FLAGS_FLOW_HANDLE_SFT))
 
 /*
  * 32 bit Flow ID handlers
diff --git a/drivers/net/bnxt/tf_core/tf_msg.c b/drivers/net/bnxt/tf_core/tf_msg.c
index 1007211363..be30d4a09f 100644
--- a/drivers/net/bnxt/tf_core/tf_msg.c
+++ b/drivers/net/bnxt/tf_core/tf_msg.c
@@ -415,7 +415,6 @@ tf_msg_session_resc_qcaps(struct tf *tfp,
 
 	/* Post process the response */
 	data = (struct tf_rm_resc_req_entry *)qcaps_buf.va_addr;
-
 	for (i = 0; i < size; i++) {
 		query[i].type = tfp_le_to_cpu_32(data[i].type);
 		query[i].min = tfp_le_to_cpu_16(data[i].min);
@@ -1462,7 +1461,7 @@ tf_msg_set_global_cfg(struct tf *tfp,
 	/* Only set mask if pointer is provided
 	 */
 	if (params->config_mask) {
-		tfp_memcpy(req.data + params->config_sz_in_bytes,
+		tfp_memcpy(req.mask,
 			   params->config_mask,
 			   params->config_sz_in_bytes);
 	}
diff --git a/drivers/net/bnxt/tf_core/tf_rm.c b/drivers/net/bnxt/tf_core/tf_rm.c
index 2c08fb80fe..19de6e4c63 100644
--- a/drivers/net/bnxt/tf_core/tf_rm.c
+++ b/drivers/net/bnxt/tf_core/tf_rm.c
@@ -486,14 +486,20 @@ tf_rm_create_db(struct tf *tfp,
 				req[j].max = parms->alloc_cnt[i];
 				j++;
 			} else {
+				const char *type_str;
+				uint16_t hcapi_type = parms->cfg[i].hcapi_type;
+
+				dev->ops->tf_dev_get_resource_str(tfp,
+								  hcapi_type,
+								  &type_str);
 				TFP_DRV_LOG(ERR,
-					    "%s: Resource failure, type:%d\n",
-					    tf_dir_2_str(parms->dir),
-					    parms->cfg[i].hcapi_type);
+					"%s: Resource failure, type:%d:%s\n",
+					tf_dir_2_str(parms->dir),
+					hcapi_type, type_str);
 				TFP_DRV_LOG(ERR,
 					"req:%d, avail:%d\n",
 					parms->alloc_cnt[i],
-					query[parms->cfg[i].hcapi_type].max);
+					query[hcapi_type].max);
 				return -EINVAL;
 			}
 		}
diff --git a/drivers/net/bnxt/tf_core/tf_shadow_tbl.c b/drivers/net/bnxt/tf_core/tf_shadow_tbl.c
index 014e4f3c83..396ebdb0a9 100644
--- a/drivers/net/bnxt/tf_core/tf_shadow_tbl.c
+++ b/drivers/net/bnxt/tf_core/tf_shadow_tbl.c
@@ -177,8 +177,6 @@ static int tf_shadow_tbl_is_searchable(enum tf_tbl_type type)
 	case TF_TBL_TYPE_ACT_SP_SMAC_IPV4:
 	case TF_TBL_TYPE_ACT_SP_SMAC_IPV6:
 	case TF_TBL_TYPE_ACT_MODIFY_IPV4:
-	case TF_TBL_TYPE_ACT_MODIFY_SPORT:
-	case TF_TBL_TYPE_ACT_MODIFY_DPORT:
 		rc = 1;
 		break;
 	default:
diff --git a/drivers/net/bnxt/tf_core/tf_util.c b/drivers/net/bnxt/tf_core/tf_util.c
index ca37df5102..74c8f26204 100644
--- a/drivers/net/bnxt/tf_core/tf_util.c
+++ b/drivers/net/bnxt/tf_core/tf_util.c
@@ -88,12 +88,8 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
 		return "Source Properties SMAC IPv6";
 	case TF_TBL_TYPE_ACT_STATS_64:
 		return "Stats 64B";
-	case TF_TBL_TYPE_ACT_MODIFY_SPORT:
-		return "NAT Source Port";
-	case TF_TBL_TYPE_ACT_MODIFY_DPORT:
-		return "NAT Destination Port";
 	case TF_TBL_TYPE_ACT_MODIFY_IPV4:
-		return "NAT IPv4";
+		return "Modify IPv4";
 	case TF_TBL_TYPE_METER_PROF:
 		return "Meter Profile";
 	case TF_TBL_TYPE_METER_INST:
@@ -116,8 +112,6 @@ tf_tbl_type_2_str(enum tf_tbl_type tbl_type)
 		return "Range";
 	case TF_TBL_TYPE_LAG:
 		return "Link Aggregation";
-	case TF_TBL_TYPE_VNIC_SVIF:
-		return "VNIC SVIF";
 	case TF_TBL_TYPE_EM_FKB:
 		return "EM Flexible Key Builder";
 	case TF_TBL_TYPE_WC_FKB:
