From patchwork Tue Jun 15 11:03:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 94224 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id C1497A0C47; Tue, 15 Jun 2021 13:04:56 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CE9A64117E; Tue, 15 Jun 2021 13:04:18 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2283341169 for ; Tue, 15 Jun 2021 13:04:17 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15FB00Ho011624; Tue, 15 Jun 2021 04:04:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=ZAOpodMP1wNlLCk4ZY11oIdmbyHZIkGyuyvfjoCEezI=; b=IB16H3S3WRS3JcIWuH216TolJGZZX+dOMam/sqqbT1Sh2BMfT0Y8gPIhe3e43VhM3jFz CqVAn4y4hN6KIHEUOWUqCOIYPw7ly/nr4fcmV8bInhDJiaVMnYtM0CNx8Ox/W0l4hMhs WVZYE6TRwmcJeWzOojQHrf80OYS/NtZ9HDC2ha8yEHV7V3kxxn8JgFL0mquY39YdmC+K c3qhg1fTjUrTvLXev46DTsq/z90NUc6p2MdfGkrWDbAAygQEZGKhMXv171bOtgu8nDwV /TdEmWXghSYptJRDpka4pXkqi7roUBHesbiB1diz0C0X+vx+kj8DKiFhbOJyrnbKPvac Sg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 396tagr4yj-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 15 Jun 2021 04:04:14 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Jun 2021 04:04:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Jun 2021 04:04:13 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id F29033F70D0; Tue, 15 Jun 2021 04:04:11 -0700 (PDT) From: Tomasz Duszynski To: Thomas Monjalon , Jakub Palider , Tomasz Duszynski , "Ray Kinsella" , Neil Horman , "Anatoly Burakov" CC: Date: Tue, 15 Jun 2021 13:03:22 +0200 Message-ID: <20210615110345.11057-10-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615110345.11057-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> <20210615110345.11057-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: A0mX2PvLYS673R1ANcL3v77G0IFTPA2E X-Proofpoint-GUID: A0mX2PvLYS673R1ANcL3v77G0IFTPA2E X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-15_04:2021-06-14, 2021-06-15 signatures=0 Subject: [dpdk-dev] [PATCH v2 09/32] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add baseband phy cgx/rpm skeleton driver which merely probes a matching device. CGX/RPM are Ethernet MACs hardwired to baseband subsystem. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- MAINTAINERS | 7 +- doc/guides/rawdevs/cnxk_bphy.rst | 23 ++++ doc/guides/rawdevs/index.rst | 1 + doc/guides/rel_notes/release_21_08.rst | 7 ++ drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 151 +++++++++++++++++++++++++ drivers/raw/cnxk_bphy/meson.build | 8 ++ drivers/raw/cnxk_bphy/version.map | 3 + drivers/raw/meson.build | 1 + usertools/dpdk-devbind.py | 4 +- 9 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c create mode 100644 drivers/raw/cnxk_bphy/meson.build create mode 100644 drivers/raw/cnxk_bphy/version.map diff --git a/MAINTAINERS b/MAINTAINERS index 5877a1697..4f533fcdb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1287,6 +1287,12 @@ M: Nipun Gupta F: drivers/raw/dpaa2_cmdif/ F: doc/guides/rawdevs/dpaa2_cmdif.rst +Marvell CNXK BPHY +M: Jakub Palider +M: Tomasz Duszynski +F: doc/guides/rawdevs/cnxk_bphy.rst +F: drivers/raw/cnxk_bphy/ + Marvell OCTEON TX2 DMA M: Radha Mohan Chintakuntla M: Veerasenareddy Burru @@ -1307,7 +1313,6 @@ F: doc/guides/rawdevs/ntb.rst F: examples/ntb/ F: doc/guides/sample_app_ug/ntb.rst - Packet processing ----------------- diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst new file mode 100644 index 000000000..96ab68435 --- /dev/null +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -0,0 +1,23 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2021 Marvell. + +Marvell CNXK BPHY Driver +======================== + +CN10K/CN9K Fusion product families offer an internal BPHY unit which provides +set of hardware accelerators for performing baseband related operations. +Connectivity to the outside world happens through a block called RFOE which is +backed by ethernet I/O block called CGX or RPM (depending on the chip version). +RFOE stands for Radio Frequency Over Ethernet and provides support for +IEEE 1904.3 (RoE) standard. + +Device Setup +------------ + +The BPHY CGX/RPM devices will need to be bound to a user-space IO driver for +use. The script ``dpdk-devbind.py`` script included with DPDK can be used to +view the state of the devices and to bind them to a suitable DPDK-supported +kernel driver. When querying the status of the devices, they will appear under +the category of "Misc (rawdev) devices", i.e. the command +``dpdk-devbind.py --status-dev misc`` can be used to see the state of those +devices alone. diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst index f64ec4427..7fbae40ea 100644 --- a/doc/guides/rawdevs/index.rst +++ b/doc/guides/rawdevs/index.rst @@ -11,6 +11,7 @@ application through rawdev API. :maxdepth: 2 :numbered: + cnxk_bphy dpaa2_cmdif dpaa2_qdma ifpga diff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst index a6ecfdf3c..ae70e15d1 100644 --- a/doc/guides/rel_notes/release_21_08.rst +++ b/doc/guides/rel_notes/release_21_08.rst @@ -55,6 +55,13 @@ New Features Also, make sure to start the actual text at the margin. ======================================================= +* **Added Baseband phy CNXK PMD.** + + Added new Baseband phy CGX/RPM PMD which is used for configuring Ethernet I/O + interfaces hardwired to Baseband phy subsystem. Configuration happens via + standard rawdev enq/deq operations. See the :doc:`../rawdevs/cnxk_bphy` + rawdev guide for more details on this driver. + Removed Items ------------- diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c new file mode 100644 index 000000000..e537888f9 --- /dev/null +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ +#include +#include +#include + +#include + +struct cnxk_bphy_cgx_queue { + unsigned int lmac; + /* queue holds up to one response */ + void *rsp; +}; + +struct cnxk_bphy_cgx { + struct roc_bphy_cgx *rcgx; + struct cnxk_bphy_cgx_queue queues[MAX_LMACS_PER_CGX]; + unsigned int num_queues; +}; + +static void +cnxk_bphy_cgx_format_name(char *name, unsigned int len, + struct rte_pci_device *pci_dev) +{ + snprintf(name, len, "BPHY_CGX:%x:%02x.%x", pci_dev->addr.bus, + pci_dev->addr.devid, pci_dev->addr.function); +} + +static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = { +}; + +static void +cnxk_bphy_cgx_init_queues(struct cnxk_bphy_cgx *cgx) +{ + struct roc_bphy_cgx *rcgx = cgx->rcgx; + unsigned int i; + + for (i = 0; i < RTE_DIM(cgx->queues); i++) { + if (!(rcgx->lmac_bmap & BIT_ULL(i))) + continue; + + cgx->queues[cgx->num_queues++].lmac = i; + } +} + +static void +cnxk_bphy_cgx_fini_queues(struct cnxk_bphy_cgx *cgx) +{ + unsigned int i; + + for (i = 0; i < cgx->num_queues; i++) { + if (cgx->queues[i].rsp) + rte_free(cgx->queues[i].rsp); + } + + cgx->num_queues = 0; +} + +static int +cnxk_bphy_cgx_rawdev_probe(struct rte_pci_driver *pci_drv, + struct rte_pci_device *pci_dev) +{ + char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct rte_rawdev *rawdev; + struct cnxk_bphy_cgx *cgx; + struct roc_bphy_cgx *rcgx; + int ret; + + RTE_SET_USED(pci_drv); + + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + if (!pci_dev->mem_resource[0].addr) + return -ENODEV; + + ret = roc_plt_init(); + if (ret) + return ret; + + cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev); + rawdev = rte_rawdev_pmd_allocate(name, sizeof(*cgx), rte_socket_id()); + if (!rawdev) + return -ENOMEM; + + rawdev->dev_ops = &cnxk_bphy_cgx_rawdev_ops; + rawdev->device = &pci_dev->device; + rawdev->driver_name = pci_dev->driver->driver.name; + + cgx = rawdev->dev_private; + cgx->rcgx = rte_zmalloc(NULL, sizeof(*rcgx), 0); + if (!cgx->rcgx) { + ret = -ENOMEM; + goto out_pmd_release; + } + + rcgx = cgx->rcgx; + rcgx->bar0_pa = pci_dev->mem_resource[0].phys_addr; + rcgx->bar0_va = pci_dev->mem_resource[0].addr; + ret = roc_bphy_cgx_dev_init(rcgx); + if (ret) + goto out_free; + + cnxk_bphy_cgx_init_queues(cgx); + + return 0; +out_free: + rte_free(rcgx); +out_pmd_release: + rte_rawdev_pmd_release(rawdev); + + return ret; +} + +static int +cnxk_bphy_cgx_rawdev_remove(struct rte_pci_device *pci_dev) +{ + char name[RTE_RAWDEV_NAME_MAX_LEN]; + struct rte_rawdev *rawdev; + struct cnxk_bphy_cgx *cgx; + + cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev); + rawdev = rte_rawdev_pmd_get_named_dev(name); + if (!rawdev) + return -ENODEV; + + cgx = rawdev->dev_private; + cnxk_bphy_cgx_fini_queues(cgx); + roc_bphy_cgx_dev_fini(cgx->rcgx); + rte_free(cgx->rcgx); + + return rte_rawdev_pmd_release(rawdev); +} + +static const struct rte_pci_id cnxk_bphy_cgx_map[] = { + {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_CGX)}, + {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM)}, + {} /* sentinel */ +}; + +static struct rte_pci_driver bphy_cgx_rawdev_pmd = { + .id_table = cnxk_bphy_cgx_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING, + .probe = cnxk_bphy_cgx_rawdev_probe, + .remove = cnxk_bphy_cgx_rawdev_remove, +}; + +RTE_PMD_REGISTER_PCI(cnxk_bphy_cgx_rawdev_pci_driver, bphy_cgx_rawdev_pmd); +RTE_PMD_REGISTER_PCI_TABLE(cnxk_bphy_cgx_rawdev_pci_driver, cnxk_bphy_cgx_map); +RTE_PMD_REGISTER_KMOD_DEP(cnxk_bphy_cgx_rawdev_pci_driver, "vfio-pci"); diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build new file mode 100644 index 000000000..78d8081fe --- /dev/null +++ b/drivers/raw/cnxk_bphy/meson.build @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2021 Marvell. +# + +deps += ['bus_pci', 'common_cnxk', 'rawdev'] +sources = files( + 'cnxk_bphy_cgx.c', +) diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map new file mode 100644 index 000000000..4a76d1d52 --- /dev/null +++ b/drivers/raw/cnxk_bphy/version.map @@ -0,0 +1,3 @@ +DPDK_21 { + local: *; +}; diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build index c33a7c5f3..b51536f8a 100644 --- a/drivers/raw/meson.build +++ b/drivers/raw/meson.build @@ -6,6 +6,7 @@ if is_windows endif drivers = [ + 'cnxk_bphy', 'dpaa2_cmdif', 'dpaa2_qdma', 'ifpga', diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py index 2fe0c6a6a..55a73961d 100755 --- a/usertools/dpdk-devbind.py +++ b/usertools/dpdk-devbind.py @@ -45,6 +45,8 @@ 'SVendor': None, 'SDevice': None} octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4', 'SVendor': None, 'SDevice': None} +cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059,a060', + 'SVendor': None, 'SDevice': None} intel_dlb = {'Class': '0b', 'Vendor': '8086', 'Device': '270b,2710,2714', 'SVendor': None, 'SDevice': None} @@ -69,7 +71,7 @@ mempool_devices = [cavium_fpa, octeontx2_npa] compress_devices = [cavium_zip] regex_devices = [octeontx2_ree] -misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr, +misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr, intel_ntb_skx, intel_ntb_icx, octeontx2_dma]