From patchwork Tue Jun 15 11:03:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Duszynski X-Patchwork-Id: 94236 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 71119A0C47; Tue, 15 Jun 2021 13:06:21 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7449541172; Tue, 15 Jun 2021 13:04:44 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 7DBB8411BD for ; Tue, 15 Jun 2021 13:04:42 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15FAxxdk011583; Tue, 15 Jun 2021 04:04:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=AoTUGXVkqTkoaD1nD73AnyqDS3zKDuMHgzzlo6fPw1c=; b=EllI/gWhy+Ghh6M2sPb1ynKs2KoVU98QvHJv6UJfFMhEVoDmtx9V36f5c1Q2NyCueeTE NsnY+Y0ZhUdVxqwuzG+TB5f8vZ+sxu4NjNrmeZChZBmmwHpDDI/tAvtvTVMD+cBtbpXO PofoDsSJGq533NaBwgvY3NlYZMoCFRMFGhOSE2Me+nHOnfxVOzra99XkqO7RDMWu6r2X yzF6jRRz3dB5O2TBvKmeeYS246ZpeVExhVf8J5g+5ysMttqdGh/Uf81hEthG0PwsZhm7 Uvg+ZhXfesTkVmDp8P08pbrT6YdLnjEfqEsHsmQfu53nwyDPYnnHeC5PgJsg1VwcHZJc dg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 396tagr53c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 15 Jun 2021 04:04:40 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Jun 2021 04:04:38 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Jun 2021 04:04:38 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 5223E3F708E; Tue, 15 Jun 2021 04:04:36 -0700 (PDT) From: Tomasz Duszynski To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman CC: , Tomasz Duszynski , Jakub Palider Date: Tue, 15 Jun 2021 13:03:34 +0200 Message-ID: <20210615110345.11057-22-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615110345.11057-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> <20210615110345.11057-1-tduszynski@marvell.com> MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: cuBmJFIQWr6e36sXfb7xjatK8pScgDTu X-Proofpoint-GUID: cuBmJFIQWr6e36sXfb7xjatK8pScgDTu X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-15_04:2021-06-14, 2021-06-15 signatures=0 Subject: [dpdk-dev] [PATCH v2 21/32] common/cnxk: support for clearing bphy irq handler X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for clearing previously register baseband phy irq handler. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 66 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 2 + drivers/common/cnxk/version.map | 1 + 3 files changed, 69 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index f988abf51..4b87fc801 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -33,6 +33,7 @@ struct roc_bphy_irq_stack { #define ROC_BPHY_IOC_MAGIC 0xF3 #define ROC_BPHY_IOC_SET_BPHY_HANDLER \ _IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data) +#define ROC_BPHY_IOC_CLR_BPHY_HANDLER _IO(ROC_BPHY_IOC_MAGIC, 2) #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t) #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t) @@ -316,3 +317,68 @@ roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num) return irq_chip->avail_irq_bmask & BIT(irq_num); } + +int +roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num) +{ + roc_cpuset_t orig_cpuset, intr_cpuset; + const struct plt_memzone *mz; + int retval; + + if (chip == NULL) + return -EINVAL; + if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0) + return -EINVAL; + if (!roc_bphy_intr_available(chip, irq_num)) + return -ENOTSUP; + if (chip->irq_vecs[irq_num].handler == NULL) + return -EINVAL; + mz = plt_memzone_lookup(chip->mz_name); + if (mz == NULL) + return -ENXIO; + + retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (retval < 0) { + plt_warn("Failed to get affinity mask"); + CPU_ZERO(&orig_cpuset); + CPU_SET(0, &orig_cpuset); + } + + CPU_ZERO(&intr_cpuset); + CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset); + retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), + &intr_cpuset); + if (retval < 0) { + plt_warn("Failed to set affinity mask"); + CPU_ZERO(&orig_cpuset); + CPU_SET(0, &orig_cpuset); + } + + retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num); + if (retval == 0) { + roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu); + chip->n_handlers--; + chip->irq_vecs[irq_num].isr_data = NULL; + chip->irq_vecs[irq_num].handler = NULL; + chip->irq_vecs[irq_num].handler_cpu = -1; + if (chip->n_handlers == 0) { + retval = plt_memzone_free(mz); + if (retval < 0) + plt_err("Failed to free memzone: irq %d", + irq_num); + } + } else { + plt_err("Failed to clear bphy interrupt handler"); + } + + retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (retval < 0) { + plt_warn("Failed to restore affinity mask"); + CPU_ZERO(&orig_cpuset); + CPU_SET(0, &orig_cpuset); + } + + return retval; +} diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index 7dd23f4ab..778764f68 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -32,5 +32,7 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, void *isr_data); __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num); +__roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, + int irq_num); #endif /* _ROC_BPHY_IRQ_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 861a97cc0..941055ba0 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -22,6 +22,7 @@ INTERNAL { roc_bphy_cgx_stop_rxtx; roc_bphy_dev_fini; roc_bphy_dev_init; + roc_bphy_handler_clear; roc_bphy_intr_available; roc_bphy_intr_fini; roc_bphy_intr_handler;