From patchwork Wed Sep 1 16:32:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bruce Richardson X-Patchwork-Id: 97707 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A0282A0C47; Wed, 1 Sep 2021 18:32:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC3FE41149; Wed, 1 Sep 2021 18:32:33 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mails.dpdk.org (Postfix) with ESMTP id AABBD4113B for ; Wed, 1 Sep 2021 18:32:32 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10094"; a="198359873" X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="198359873" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Sep 2021 09:32:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,369,1620716400"; d="scan'208";a="645812761" Received: from silpixa00399126.ir.intel.com ([10.237.223.29]) by orsmga005.jf.intel.com with ESMTP; 01 Sep 2021 09:32:30 -0700 From: Bruce Richardson To: dev@dpdk.org Cc: conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com, jerinj@marvell.com, Bruce Richardson Date: Wed, 1 Sep 2021 17:32:12 +0100 Message-Id: <20210901163216.120087-3-bruce.richardson@intel.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210901163216.120087-1-bruce.richardson@intel.com> References: <20210826183301.333442-1-bruce.richardson@intel.com> <20210901163216.120087-1-bruce.richardson@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH v2 2/6] app/test: add basic dmadev instance tests X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Run basic sanity tests for configuring, starting and stopping a dmadev instance to help validate drivers. This also provides the framework for future tests for data-path operation. Signed-off-by: Bruce Richardson Reviewed-by: Conor Walsh --- app/test/test_dmadev.c | 81 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c index bb01e86483..12f7c69629 100644 --- a/app/test/test_dmadev.c +++ b/app/test/test_dmadev.c @@ -2,6 +2,7 @@ * Copyright(c) 2021 HiSilicon Limited. * Copyright(c) 2021 Intel Corporation. */ +#include #include #include @@ -13,6 +14,77 @@ /* from test_dmadev_api.c */ extern int test_dmadev_api(uint16_t dev_id); +#define PRINT_ERR(...) print_err(__func__, __LINE__, __VA_ARGS__) + +static inline int +__rte_format_printf(3, 4) +print_err(const char *func, int lineno, const char *format, ...) +{ + va_list ap; + int ret; + + ret = fprintf(stderr, "In %s:%d - ", func, lineno); + va_start(ap, format); + ret += vfprintf(stderr, format, ap); + va_end(ap); + + return ret; +} + +static int +test_dmadev_instance(uint16_t dev_id) +{ +#define TEST_RINGSIZE 512 + struct rte_dmadev_stats stats; + struct rte_dmadev_info info; + const struct rte_dmadev_conf conf = { .nb_vchans = 1}; + const struct rte_dmadev_vchan_conf qconf = { + .direction = RTE_DMA_DIR_MEM_TO_MEM, + .nb_desc = TEST_RINGSIZE, + }; + const int vchan = 0; + + printf("\n### Test dmadev instance %u\n", dev_id); + + rte_dmadev_info_get(dev_id, &info); + if (info.max_vchans < 1) { + PRINT_ERR("Error, no channels available on device id %u\n", dev_id); + return -1; + } + if (rte_dmadev_configure(dev_id, &conf) != 0) { + PRINT_ERR("Error with rte_dmadev_configure()\n"); + return -1; + } + if (rte_dmadev_vchan_setup(dev_id, vchan, &qconf) < 0) { + PRINT_ERR("Error with queue configuration\n"); + return -1; + } + + rte_dmadev_info_get(dev_id, &info); + if (info.nb_vchans != 1) { + PRINT_ERR("Error, no configured queues reported on device id %u\n", dev_id); + return -1; + } + + if (rte_dmadev_start(dev_id) != 0) { + PRINT_ERR("Error with rte_dmadev_start()\n"); + return -1; + } + if (rte_dmadev_stats_get(dev_id, vchan, &stats) != 0) { + PRINT_ERR("Error with rte_dmadev_stats_get()\n"); + return -1; + } + if (stats.completed != 0 || stats.submitted != 0 || stats.errors != 0) { + PRINT_ERR("Error device stats are not all zero: completed = %"PRIu64", submitted = %"PRIu64", errors = %"PRIu64"\n", + stats.completed, stats.submitted, stats.errors); + return -1; + } + + rte_dmadev_stop(dev_id); + rte_dmadev_stats_reset(dev_id, vchan); + return 0; +} + static int test_apis(void) { @@ -35,10 +107,19 @@ test_apis(void) static int test_dmadev(void) { + int i; + /* basic sanity on dmadev infrastructure */ if (test_apis() < 0) return -1; + if (rte_dmadev_count() == 0) + return TEST_SKIPPED; + + for (i = 0; i < RTE_DMADEV_MAX_DEVS; i++) + if (rte_dmadevices[i].state == RTE_DMADEV_ATTACHED && test_dmadev_instance(i) < 0) + return -1; + return 0; }