From patchwork Fri Sep 10 08:08:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 98562 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 64233A0547; Fri, 10 Sep 2021 10:27:25 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6343C4113D; Fri, 10 Sep 2021 10:27:06 +0200 (CEST) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id D868C41135 for ; Fri, 10 Sep 2021 10:27:02 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10102"; a="221061056" X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="221061056" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Sep 2021 01:27:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,282,1624345200"; d="scan'208";a="540346438" Received: from wuwenjun.sh.intel.com ([10.67.110.178]) by FMSMGA003.fm.intel.com with ESMTP; 10 Sep 2021 01:27:01 -0700 From: Wenjun Wu To: dev@dpdk.org, qi.z.zhang@intel.com Cc: Wenjun Wu , Steve Yang Date: Fri, 10 Sep 2021 16:08:20 +0800 Message-Id: <20210910080821.18718-7-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210910080821.18718-1-wenjun1.wu@intel.com> References: <20210910080821.18718-1-wenjun1.wu@intel.com> MIME-Version: 1.0 Subject: [dpdk-dev] [PATCH 20.11 6/7] net/ice: add L4 support for QinQ switch filter X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch is not for LTS upstream, just for users to cherry-pick. Add L4 support for QinQ switch filter as following flow patterns: eth / vlan / vlan / ipv4 / udp eth / vlan / vlan / ipv4 / tcp eth / vlan / vlan / ipv6 / udp eth / vlan / vlan / ipv6 / tcp Signed-off-by: Steve Yang Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_switch_filter.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index 45fa9723d2..eed72d9446 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -44,6 +44,12 @@ ICE_INSET_IPV4_PROTO | ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS) #define ICE_SW_INSET_MAC_QINQ_IPV4 ( \ ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV4) +#define ICE_SW_INSET_MAC_QINQ_IPV4_TCP ( \ + ICE_SW_INSET_MAC_QINQ_IPV4 | \ + ICE_INSET_TCP_DST_PORT | ICE_INSET_TCP_SRC_PORT) +#define ICE_SW_INSET_MAC_QINQ_IPV4_UDP ( \ + ICE_SW_INSET_MAC_QINQ_IPV4 | \ + ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT) #define ICE_SW_INSET_MAC_IPV4_TCP ( \ ICE_INSET_DMAC | ICE_INSET_IPV4_DST | ICE_INSET_IPV4_SRC | \ ICE_INSET_IPV4_TTL | ICE_INSET_IPV4_TOS | \ @@ -58,6 +64,12 @@ ICE_INSET_IPV6_NEXT_HDR) #define ICE_SW_INSET_MAC_QINQ_IPV6 ( \ ICE_SW_INSET_MAC_QINQ | ICE_SW_INSET_MAC_IPV6) +#define ICE_SW_INSET_MAC_QINQ_IPV6_TCP ( \ + ICE_SW_INSET_MAC_QINQ_IPV6 | \ + ICE_INSET_TCP_DST_PORT | ICE_INSET_TCP_SRC_PORT) +#define ICE_SW_INSET_MAC_QINQ_IPV6_UDP ( \ + ICE_SW_INSET_MAC_QINQ_IPV6 | \ + ICE_INSET_UDP_DST_PORT | ICE_INSET_UDP_SRC_PORT) #define ICE_SW_INSET_MAC_IPV6_TCP ( \ ICE_INSET_DMAC | ICE_INSET_IPV6_DST | ICE_INSET_IPV6_SRC | \ ICE_INSET_IPV6_HOP_LIMIT | ICE_INSET_IPV6_TC | \ @@ -274,8 +286,16 @@ ice_pattern_match_item ice_switch_pattern_dist_comms[] = { ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv4_tcp, + ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv4_udp, + ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE}, {pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv6_tcp, + ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv6_udp, + ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes_proto, @@ -410,8 +430,16 @@ ice_pattern_match_item ice_switch_pattern_perm_comms[] = { ICE_INSET_NONE, ICE_INSET_NONE}, {pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv4_tcp, + ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv4_udp, + ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE}, {pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv6_tcp, + ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE}, + {pattern_eth_qinq_ipv6_udp, + ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE}, {pattern_eth_qinq_pppoes_proto,