@@ -766,6 +766,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
flow_counters_dump);
+ attr->log_max_rmp = MLX5_GET(cmd_hca_cap, hcattr, log_max_rmp);
+ attr->mem_rq_rmp = MLX5_GET(cmd_hca_cap, hcattr, mem_rq_rmp);
attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
log_max_rqt_size);
attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
@@ -1277,6 +1279,56 @@ mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
}
/**
+ * Create RMP using DevX API.
+ *
+ * @param[in] ctx
+ * Context returned from mlx5 open_device() glue function.
+ * @param [in] rmp_attr
+ * Pointer to create RMP attributes structure.
+ * @param [in] socket
+ * CPU socket ID for allocations.
+ *
+ * @return
+ * The DevX object created, NULL otherwise and rte_errno is set.
+ */
+struct mlx5_devx_obj *
+mlx5_devx_cmd_create_rmp(void *ctx,
+ struct mlx5_devx_create_rmp_attr *rmp_attr,
+ int socket)
+{
+ uint32_t in[MLX5_ST_SZ_DW(create_rmp_in)] = {0};
+ uint32_t out[MLX5_ST_SZ_DW(create_rmp_out)] = {0};
+ void *rmp_ctx, *wq_ctx;
+ struct mlx5_devx_wq_attr *wq_attr;
+ struct mlx5_devx_obj *rmp = NULL;
+
+ rmp = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rmp), 0, socket);
+ if (!rmp) {
+ DRV_LOG(ERR, "Failed to allocate RMP data");
+ rte_errno = ENOMEM;
+ return NULL;
+ }
+ MLX5_SET(create_rmp_in, in, opcode, MLX5_CMD_OP_CREATE_RMP);
+ rmp_ctx = MLX5_ADDR_OF(create_rmp_in, in, ctx);
+ MLX5_SET(rmpc, rmp_ctx, state, rmp_attr->state);
+ MLX5_SET(rmpc, rmp_ctx, basic_cyclic_rcv_wqe,
+ rmp_attr->basic_cyclic_rcv_wqe);
+ wq_ctx = MLX5_ADDR_OF(rmpc, rmp_ctx, wq);
+ wq_attr = &rmp_attr->wq_attr;
+ devx_cmd_fill_wq_data(wq_ctx, wq_attr);
+ rmp->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
+ sizeof(out));
+ if (!rmp->obj) {
+ DRV_LOG(ERR, "Failed to create RMP using DevX");
+ rte_errno = errno;
+ mlx5_free(rmp);
+ return NULL;
+ }
+ rmp->id = MLX5_GET(create_rmp_out, out, rmpn);
+ return rmp;
+}
+
+/*
* Create TIR using DevX API.
*
* @param[in] ctx
@@ -93,6 +93,8 @@ struct mlx5_hca_flow_attr {
struct mlx5_hca_attr {
uint32_t eswitch_manager:1;
uint32_t flow_counters_dump:1;
+ uint32_t mem_rq_rmp:1;
+ uint32_t log_max_rmp:5;
uint32_t log_max_rqt_size:5;
uint32_t parse_graph_flex_node:1;
uint8_t flow_counter_bulk_alloc_bitmap;
@@ -259,6 +261,17 @@ struct mlx5_devx_modify_rq_attr {
uint32_t lwm:16; /* Contained WQ lwm. */
};
+/* Create RMP attributes structure, used by create RMP operation. */
+struct mlx5_devx_create_rmp_attr {
+ uint32_t rsvd0:8;
+ uint32_t state:4;
+ uint32_t rsvd1:20;
+ uint32_t basic_cyclic_rcv_wqe:1;
+ uint32_t rsvd4:31;
+ uint32_t rsvd8[10];
+ struct mlx5_devx_wq_attr wq_attr;
+};
+
struct mlx5_rx_hash_field_select {
uint32_t l3_prot_type:1;
uint32_t l4_prot_type:1;
@@ -536,6 +549,9 @@ __rte_internal
int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
struct mlx5_devx_modify_rq_attr *rq_attr);
__rte_internal
+struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx,
+ struct mlx5_devx_create_rmp_attr *rq_attr, int socket);
+__rte_internal
struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
struct mlx5_devx_tir_attr *tir_attr);
__rte_internal
@@ -1062,6 +1062,10 @@ enum {
MLX5_CMD_OP_CREATE_RQ = 0x908,
MLX5_CMD_OP_MODIFY_RQ = 0x909,
MLX5_CMD_OP_QUERY_RQ = 0x90b,
+ MLX5_CMD_OP_CREATE_RMP = 0x90c,
+ MLX5_CMD_OP_MODIFY_RMP = 0x90d,
+ MLX5_CMD_OP_DESTROY_RMP = 0x90e,
+ MLX5_CMD_OP_QUERY_RMP = 0x90f,
MLX5_CMD_OP_CREATE_TIS = 0x912,
MLX5_CMD_OP_QUERY_TIS = 0x915,
MLX5_CMD_OP_CREATE_RQT = 0x916,
@@ -1561,7 +1565,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 reserved_at_378[0x3];
u8 log_max_tis[0x5];
u8 basic_cyclic_rcv_wqe[0x1];
- u8 reserved_at_381[0x2];
+ u8 reserved_at_381[0x1];
+ u8 mem_rq_rmp[0x1];
u8 log_max_rmp[0x5];
u8 reserved_at_388[0x3];
u8 log_max_rqt[0x5];
@@ -2209,6 +2214,84 @@ struct mlx5_ifc_query_rq_in_bits {
u8 reserved_at_60[0x20];
};
+enum {
+ MLX5_RMPC_STATE_RDY = 0x1,
+ MLX5_RMPC_STATE_ERR = 0x3,
+};
+
+struct mlx5_ifc_rmpc_bits {
+ u8 reserved_at_0[0x8];
+ u8 state[0x4];
+ u8 reserved_at_c[0x14];
+ u8 basic_cyclic_rcv_wqe[0x1];
+ u8 reserved_at_21[0x1f];
+ u8 reserved_at_40[0x140];
+ struct mlx5_ifc_wq_bits wq;
+};
+
+struct mlx5_ifc_query_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0xc0];
+ struct mlx5_ifc_rmpc_bits rmp_context;
+};
+
+struct mlx5_ifc_query_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 reserved_at_10[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0x8];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_modify_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_rmp_bitmask_bits {
+ u8 reserved_at_0[0x20];
+ u8 reserved_at_20[0x1f];
+ u8 lwm[0x1];
+};
+
+struct mlx5_ifc_modify_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 rmp_state[0x4];
+ u8 reserved_at_44[0x4];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+ struct mlx5_ifc_rmp_bitmask_bits bitmask;
+ u8 reserved_at_c0[0x40];
+ struct mlx5_ifc_rmpc_bits ctx;
+};
+
+struct mlx5_ifc_create_rmp_out_bits {
+ u8 status[0x8];
+ u8 reserved_at_8[0x18];
+ u8 syndrome[0x20];
+ u8 reserved_at_40[0x8];
+ u8 rmpn[0x18];
+ u8 reserved_at_60[0x20];
+};
+
+struct mlx5_ifc_create_rmp_in_bits {
+ u8 opcode[0x10];
+ u8 uid[0x10];
+ u8 reserved_at_20[0x10];
+ u8 op_mod[0x10];
+ u8 reserved_at_40[0xc0];
+ struct mlx5_ifc_rmpc_bits ctx;
+};
+
struct mlx5_ifc_create_tis_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
@@ -30,6 +30,7 @@ INTERNAL {
mlx5_devx_cmd_create_geneve_tlv_option;
mlx5_devx_cmd_create_import_kek_obj;
mlx5_devx_cmd_create_qp;
+ mlx5_devx_cmd_create_rmp;
mlx5_devx_cmd_create_rq;
mlx5_devx_cmd_create_rqt;
mlx5_devx_cmd_create_sq;