From patchwork Thu Nov 4 21:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Khaparde X-Patchwork-Id: 103805 X-Patchwork-Delegate: ajit.khaparde@broadcom.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A1A51A0C5E; Thu, 4 Nov 2021 23:01:11 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BB7642808; Thu, 4 Nov 2021 22:59:24 +0100 (CET) Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by mails.dpdk.org (Postfix) with ESMTP id 80AFA427F2 for ; Thu, 4 Nov 2021 22:59:18 +0100 (CET) Received: by mail-pl1-f174.google.com with SMTP id t11so9519438plq.11 for ; Thu, 04 Nov 2021 14:59:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=oRyzOqdO3VpxYKq/IafPVlzQZreciqfqtUep92ISAgQ=; b=MAQkfLC8rxty60ZX6bHmxXu/t5CRQ4HC5u798FDQ+bheSKOe1JuBi4kVnzIc2Sml55 jMLPXjnKrXjfw7WxhAxXZkTsUGaYOnWeSICxD28D9MY3z4TyNzttWyhuE/F6dLzEfibT x6SDFg5YfLT8Mb1xiASdo+bTMDfwMtcyheYqI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=oRyzOqdO3VpxYKq/IafPVlzQZreciqfqtUep92ISAgQ=; b=cI8g5vykvh19nCsAyrkaBlS0fpjWuse+aS1ukKXVDEnTGqV8sf+MZ7jlEq/CgaSEVO xYQP0AZkWR9Cs9SC8nt4zBGQOV03+O+ppJjeOf7QW6U1TAu4oyCAg3qyi+hJY+EH3Uha 1aDQPxjkUgxWnydQiSdBIgZ+unFA4b99PjiJwDIN/tX9R8kEexrT5Z0emEtm3mnkwODe y5QuLeDJnwiA2kVaPrgsiajCQhxOxVP6/lfBfI2VEJ5CsH0rLzIr34sW1mtlm+Ffzhgv gmay7Vp419eszlOuuIjA6xR9SuHaZr1bItjf5jydnNCLS4eKg24yJPL+tTIO4VN2bkP8 4GBQ== X-Gm-Message-State: AOAM533cEP5OwgpQ3DIIGzNNjv41f5zHsI99gW6DAy/hM//WprEcjUMN 7RR/5XC5aAEVt6VJQ7E6eX0yuh6/rrr3sfwMOzb7Jmo9gEcWTzP6gU2IaeqgkuGTwb2KP7vts5c 7tSIm4wu1FOBDUjB9V+/gTY2BQHsBSKX5IxG2bZfg3AyJAicHkk5X9ZtTEmIk0lQ= X-Google-Smtp-Source: ABdhPJzvYpjKEasVORoyh9d8udb+LWTDuTrUnVEjvMX2h7J9QnOx3cYhGYexox71x00kEifpHoWiHw== X-Received: by 2002:a17:90b:3890:: with SMTP id mu16mr14760349pjb.73.1636063157537; Thu, 04 Nov 2021 14:59:17 -0700 (PDT) Received: from C02GC2QQMD6T.wifi.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id pg5sm8532242pjb.26.2021.11.04.14.59.16 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Nov 2021 14:59:16 -0700 (PDT) From: Ajit Khaparde To: dev@dpdk.org Cc: Jay Ding , Venkat Duvvuru , Farah Smith , Randy Schacher Date: Thu, 4 Nov 2021 14:58:43 -0700 Message-Id: <20211104215846.58672-20-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.30.1 (Apple Git-130) In-Reply-To: <20211104215846.58672-1-ajit.khaparde@broadcom.com> References: <20211103005251.25524-1-ajit.khaparde@broadcom.com> <20211104215846.58672-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.29 Subject: [dpdk-dev] [PATCH v5 19/22] net/bnxt: add Tx TruFlow table config for P4 device X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jay Ding Add TX direction TruFlow table type config to be compatible with other devices. For P4 device, the TX cfg is duplicated from RX. Signed-off-by: Jay Ding Signed-off-by: Venkat Duvvuru Reviewed-by: Farah Smith Reviewed-by: Randy Schacher Acked-by: Ajit Khaparde --- drivers/net/bnxt/tf_core/tf_device.c | 4 +- drivers/net/bnxt/tf_core/tf_device_p4.c | 107 ++++++++++++++++++++++++ drivers/net/bnxt/tf_core/tf_device_p4.h | 58 +------------ 3 files changed, 111 insertions(+), 58 deletions(-) diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c index 40db546604..4c416270b6 100644 --- a/drivers/net/bnxt/tf_core/tf_device.c +++ b/drivers/net/bnxt/tf_core/tf_device.c @@ -131,11 +131,11 @@ tf_dev_bind_p4(struct tf *tfp, } rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX, - tf_tbl_p4, + tf_tbl_p4[TF_DIR_RX], (uint16_t *)resources->tbl_cnt); if (rsv_cnt) { tbl_cfg.num_elements = TF_TBL_TYPE_MAX; - tbl_cfg.cfg = tf_tbl_p4; + tbl_cfg.cfg = tf_tbl_p4[TF_DIR_RX]; tbl_cfg.resources = resources; rc = tf_tbl_bind(tfp, &tbl_cfg); if (rc) { diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c index 244bd08914..a6a59b8a07 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.c +++ b/drivers/net/bnxt/tf_core/tf_device_p4.c @@ -59,6 +59,113 @@ const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = { [CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope", }; +struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = { + [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, + 0, 0 + }, + [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = { + TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, + 0, 0 + }, +}; + /** * Device specific function that retrieves the MAX number of HCAPI * types the device supports. diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h index e84c0f9e83..86de525995 100644 --- a/drivers/net/bnxt/tf_core/tf_device_p4.h +++ b/drivers/net/bnxt/tf_core/tf_device_p4.h @@ -12,6 +12,8 @@ #include "tf_if_tbl.h" #include "tf_global_cfg.h" +extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX]; + struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = { [TF_IDENT_TYPE_L2_CTXT_HIGH] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH, @@ -58,62 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = { }, }; -struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = { - [TF_TBL_TYPE_FULL_ACT_RECORD] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION, - 0, 0 - }, - [TF_TBL_TYPE_MCAST_GROUPS] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_8B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_16B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_ENCAP_64B] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6, - 0, 0 - }, - [TF_TBL_TYPE_ACT_STATS_64] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B, - 0, 0 - }, - [TF_TBL_TYPE_ACT_MODIFY_IPV4] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4, - 0, 0 - }, - [TF_TBL_TYPE_METER_PROF] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF, - 0, 0 - }, - [TF_TBL_TYPE_METER_INST] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER, - 0, 0 - }, - [TF_TBL_TYPE_MIRROR_CONFIG] = { - TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR, - 0, 0 - }, - -}; - struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = { [TF_EM_TBL_TYPE_TBL_SCOPE] = { TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,