From patchwork Thu Nov 11 06:38:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenjun Wu X-Patchwork-Id: 104169 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 56F90A0548; Thu, 11 Nov 2021 07:58:11 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0B42040E28; Thu, 11 Nov 2021 07:58:11 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 08EA740E03 for ; Thu, 11 Nov 2021 07:58:09 +0100 (CET) X-IronPort-AV: E=McAfee;i="6200,9189,10164"; a="296301501" X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="296301501" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2021 22:58:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,225,1631602800"; d="scan'208";a="670146385" Received: from wuwenjun.sh.intel.com ([10.67.110.173]) by orsmga005.jf.intel.com with ESMTP; 10 Nov 2021 22:58:07 -0800 From: Wenjun Wu To: dev@dpdk.org, qi.z.zhang@intel.com Cc: Wenjun Wu Subject: [PATCH v1] net/ice: support max burst size configuration Date: Thu, 11 Nov 2021 14:38:37 +0800 Message-Id: <20211111063837.752509-1-wenjun1.wu@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch adds support for max burst size configuration for TX scheduler. This feature can be tuned on by devargs: -a 0000:18:00.0,max_burst_size=x The value of x should between 64 and 1023*1024. Signed-off-by: Wenjun Wu --- drivers/net/ice/ice_ethdev.c | 36 ++++++++++++++++++++++++++++++++++++ drivers/net/ice/ice_ethdev.h | 1 + 2 files changed, 37 insertions(+) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 13a7a9702a..2ba42840e2 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -32,6 +32,7 @@ #define ICE_HW_DEBUG_MASK_ARG "hw_debug_mask" #define ICE_ONE_PPS_OUT_ARG "pps_out" #define ICE_RX_LOW_LATENCY_ARG "rx_low_latency" +#define ICE_MAX_BURST_SIZE_ARG "max_burst_size" #define ICE_CYCLECOUNTER_MASK 0xffffffffffffffffULL @@ -45,6 +46,7 @@ static const char * const ice_valid_args[] = { ICE_HW_DEBUG_MASK_ARG, ICE_ONE_PPS_OUT_ARG, ICE_RX_LOW_LATENCY_ARG, + ICE_MAX_BURST_SIZE_ARG, NULL }; @@ -1943,6 +1945,25 @@ handle_pps_out_arg(__rte_unused const char *key, const char *value, return 0; } +static int +parse_u16(const char *key, const char *value, void *args) +{ + u16 *num = (u16 *)args; + u16 tmp; + + errno = 0; + tmp = strtoull(value, NULL, 10); + if (errno) { + PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u16", + key, value); + return -1; + } + + *num = tmp; + + return 0; +} + static int ice_parse_devargs(struct rte_eth_dev *dev) { struct ice_adapter *ad = @@ -1991,6 +2012,13 @@ static int ice_parse_devargs(struct rte_eth_dev *dev) ret = rte_kvargs_process(kvlist, ICE_RX_LOW_LATENCY_ARG, &parse_bool, &ad->devargs.rx_low_latency); + if (ret) + goto bail; + + ret = rte_kvargs_process(kvlist, ICE_MAX_BURST_SIZE_ARG, + &parse_u16, &ad->devargs.max_burst_size); + if (ret) + goto bail; bail: rte_kvargs_free(kvlist); @@ -2199,6 +2227,14 @@ ice_dev_init(struct rte_eth_dev *dev) ice_init_controlq_parameter(hw); + if (ad->devargs.max_burst_size) { + ret = ice_cfg_rl_burst_size(hw, ad->devargs.max_burst_size); + if (ret) { + PMD_INIT_LOG(ERR, "Failed to configure burst size"); + return -EINVAL; + } + } + ret = ice_init_hw(hw); if (ret) { PMD_INIT_LOG(ERR, "Failed to initialize HW"); diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 3a5bb9bbc6..005bb25535 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -490,6 +490,7 @@ struct ice_devargs { uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; uint8_t pin_idx; uint8_t pps_out_ena; + uint16_t max_burst_size; }; /**