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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4690.15 via Frontend Transport; Fri, 12 Nov 2021 12:42:57 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 12 Nov 2021 12:42:54 +0000 From: Jiawei Wang To: , , , "Yongseok Koh" , Ori Kam CC: , , Subject: [PATCH v3] net/mlx5: fix the NIC egress flow mismatch in switchdev mode Date: Fri, 12 Nov 2021 14:42:35 +0200 Message-ID: <20211112124235.9191-1-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20211105084051.20159-1-jiaweiw@nvidia.com> References: <20211105084051.20159-1-jiaweiw@nvidia.com> MIME-Version: 1.0 X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cf703750-1f89-4c5d-89ef-08d9a5d9f412 X-MS-TrafficTypeDiagnostic: CH0PR12MB5235: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(1076003)(82310400003)(6286002)(70586007)(2616005)(26005)(70206006)(316002)(508600001)(83380400001)(8676002)(336012)(186003)(16526019)(86362001)(426003)(55016002)(7696005)(4326008)(6666004)(450100002)(36860700001)(2906002)(5660300002)(36756003)(7636003)(8936002)(54906003)(47076005)(110136005)(356005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Nov 2021 12:42:57.0348 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf703750-1f89-4c5d-89ef-08d9a5d9f412 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5235 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When E-Switch mode was enabled, the NIC egress flows was implicitly appended with source vport to match on. If the metadata register C0 was used to maintain the source vport, it was initialized to zero on packet steering engine entry, the flow could be hit only if source vport was zero, the register C0 of the packet was not correct to match in the TX side, this caused egress flow misses. This patch: - removes the implicit source vport match for NIC egress flow. - rejects the NIC egress flows on the representor ports at validation. - allows the internal NIC egress flows containing the TX_QUEUE items in order to not impact hairpins. Fixes: ce777b147bf8 ("net/mlx5: fix E-Switch flow without port item") Cc: stable@dpdk.org Signed-off-by: Jiawei Wang Acked-by: Viacheslav Ovsiienko Acked-by: Ori Kam --- v3: update the tx_item checking v2: fix one typo --- doc/guides/nics/mlx5.rst | 2 ++ drivers/net/mlx5/mlx5_flow_dv.c | 24 ++++++++++++++++++++---- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index 043d006a2b..267d25ebb8 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -493,6 +493,8 @@ Limitations completions, the scheduled send timestamps should not be specified with non-zero msb +- The NIC Egress flow on representor port is not supported. + Statistics ---------- diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 28911d6f0f..201f04ca84 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7164,8 +7164,10 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, return ret; last_item = MLX5_FLOW_ITEM_TAG; break; - case MLX5_RTE_FLOW_ITEM_TYPE_TAG: case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE: + last_item = MLX5_FLOW_ITEM_TX_QUEUE; + break; + case MLX5_RTE_FLOW_ITEM_TYPE_TAG: break; case RTE_FLOW_ITEM_TYPE_GTP: ret = flow_dv_validate_item_gtp(dev, items, item_flags, @@ -7999,6 +8001,18 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, NULL, "sample before modify action is not supported"); + /* + * Validation the NIC Egress flow on representor, except implicit + * hairpin default egress flow with TX_QUEUE item, other flows not + * work due to metadata regC0 mismatch. + */ + if ((!attr->transfer && attr->egress) && priv->representor && + !(item_flags & MLX5_FLOW_ITEM_TX_QUEUE)) + return rte_flow_error_set(error, EINVAL, + RTE_FLOW_ERROR_TYPE_ITEM, + NULL, + "NIC egress rules on representors" + " is not supported"); return 0; } @@ -13563,11 +13577,13 @@ flow_dv_translate(struct rte_eth_dev *dev, /* * When E-Switch mode is enabled, we have two cases where we need to * set the source port manually. - * The first one, is in case of Nic steering rule, and the second is - * E-Switch rule where no port_id item was found. In both cases - * the source port is set according the current port in use. + * The first one, is in case of NIC ingress steering rule, and the + * second is E-Switch rule where no port_id item was found. + * In both cases the source port is set according the current port + * in use. */ if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && + !(attr->egress && !attr->transfer) && (priv->representor || priv->master)) { if (flow_dv_translate_item_port_id(dev, match_mask, match_value, NULL, attr))