diff mbox series

[V2,4/4] pipeline: add drop port for each pipeline

Message ID 20211127000254.36148-4-cristian.dumitrescu@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series [V2,1/4] pipeline: improve the drop instruction |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS
ci/github-robot: build success github build: passed
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-aarch64-unit-testing success Testing PASS
ci/iol-x86_64-unit-testing success Testing PASS

Commit Message

Cristian Dumitrescu Nov. 27, 2021, 12:02 a.m. UTC 
  An additional output port is now implicitly created for every pipeline
to serve as the packet drop port. Up to now, the drop port had to be
explicitly created for each pipeline.

Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Signed-off-by: Yogesh Jangra <yogesh.jangra@intel.com>
---
 examples/pipeline/cli.c                   | 15 +++++++++++----
 examples/pipeline/examples/fib.cli        |  1 -
 examples/pipeline/examples/learner.cli    |  1 -
 examples/pipeline/examples/selector.cli   |  1 -
 examples/pipeline/examples/varbit.cli     |  1 -
 examples/pipeline/examples/vxlan.cli      |  1 -
 examples/pipeline/examples/vxlan_pcap.cli |  1 -
 lib/pipeline/rte_swx_pipeline.c           | 11 +++++++++++
 8 files changed, 22 insertions(+), 10 deletions(-)

Comments

Thomas Monjalon Feb. 13, 2022, 7:48 p.m. UTC | #1 
27/11/2021 01:02, Cristian Dumitrescu:
> An additional output port is now implicitly created for every pipeline
> to serve as the packet drop port. Up to now, the drop port had to be
> explicitly created for each pipeline.
> 
> Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
> Signed-off-by: Yogesh Jangra <yogesh.jangra@intel.com>

Series applied, thanks.
diff mbox series

Patch

diff --git a/examples/pipeline/cli.c b/examples/pipeline/cli.c
index 83b460caf6..c32349e5f0 100644
--- a/examples/pipeline/cli.c
+++ b/examples/pipeline/cli.c
@@ -2551,10 +2551,17 @@  cmd_pipeline_stats(char **tokens,
 
 		rte_swx_ctl_pipeline_port_out_stats_read(p->p, i, &stats);
 
-		snprintf(out, out_size, "\tPort %u:"
-			" packets %" PRIu64
-			" bytes %" PRIu64 "\n",
-			i, stats.n_pkts, stats.n_bytes);
+		if (i != info.n_ports_out - 1)
+			snprintf(out, out_size, "\tPort %u:"
+				" packets %" PRIu64
+				" bytes %" PRIu64 "\n",
+				i, stats.n_pkts, stats.n_bytes);
+		else
+			snprintf(out, out_size, "\tDROP:"
+				" packets %" PRIu64
+				" bytes %" PRIu64 "\n",
+				stats.n_pkts, stats.n_bytes);
+
 		out_size -= strlen(out);
 		out += strlen(out);
 	}
diff --git a/examples/pipeline/examples/fib.cli b/examples/pipeline/examples/fib.cli
index b20aed3cf6..93ab2b08f8 100644
--- a/examples/pipeline/examples/fib.cli
+++ b/examples/pipeline/examples/fib.cli
@@ -25,7 +25,6 @@  pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
 
 pipeline PIPELINE0 build ./examples/pipeline/examples/fib.spec
 
diff --git a/examples/pipeline/examples/learner.cli b/examples/pipeline/examples/learner.cli
index af7792624f..688ce34f34 100644
--- a/examples/pipeline/examples/learner.cli
+++ b/examples/pipeline/examples/learner.cli
@@ -25,7 +25,6 @@  pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
 
 pipeline PIPELINE0 build ./examples/pipeline/examples/learner.spec
 
diff --git a/examples/pipeline/examples/selector.cli b/examples/pipeline/examples/selector.cli
index 36f3ead541..123782c57b 100644
--- a/examples/pipeline/examples/selector.cli
+++ b/examples/pipeline/examples/selector.cli
@@ -19,7 +19,6 @@  pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
 
 pipeline PIPELINE0 build ./examples/pipeline/examples/selector.spec
 
diff --git a/examples/pipeline/examples/varbit.cli b/examples/pipeline/examples/varbit.cli
index 0589e32c15..9caeb9ca26 100644
--- a/examples/pipeline/examples/varbit.cli
+++ b/examples/pipeline/examples/varbit.cli
@@ -25,7 +25,6 @@  pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
 
 pipeline PIPELINE0 build ./examples/pipeline/examples/varbit.spec
 
diff --git a/examples/pipeline/examples/vxlan.cli b/examples/pipeline/examples/vxlan.cli
index a3bde6a9f9..444f3f7bd8 100644
--- a/examples/pipeline/examples/vxlan.cli
+++ b/examples/pipeline/examples/vxlan.cli
@@ -19,7 +19,6 @@  pipeline PIPELINE0 port out 0 link LINK0 txq 0 bsz 32
 pipeline PIPELINE0 port out 1 link LINK1 txq 0 bsz 32
 pipeline PIPELINE0 port out 2 link LINK2 txq 0 bsz 32
 pipeline PIPELINE0 port out 3 link LINK3 txq 0 bsz 32
-pipeline PIPELINE0 port out 4 sink none
 
 pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec
 pipeline PIPELINE0 table vxlan_table add ./examples/pipeline/examples/vxlan_table.txt
diff --git a/examples/pipeline/examples/vxlan_pcap.cli b/examples/pipeline/examples/vxlan_pcap.cli
index c03dc9303d..83fca8d0d9 100644
--- a/examples/pipeline/examples/vxlan_pcap.cli
+++ b/examples/pipeline/examples/vxlan_pcap.cli
@@ -14,7 +14,6 @@  pipeline PIPELINE0 port out 0 sink none
 pipeline PIPELINE0 port out 1 sink none
 pipeline PIPELINE0 port out 2 sink none
 pipeline PIPELINE0 port out 3 sink none
-pipeline PIPELINE0 port out 4 sink none
 
 pipeline PIPELINE0 build ./examples/pipeline/examples/vxlan.spec
 pipeline PIPELINE0 table vxlan_table add ./examples/pipeline/examples/vxlan_table.txt
diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c
index dd914fd935..c332d44bd1 100644
--- a/lib/pipeline/rte_swx_pipeline.c
+++ b/lib/pipeline/rte_swx_pipeline.c
@@ -9199,6 +9199,9 @@  pipeline_compile(struct rte_swx_pipeline *p);
 int
 rte_swx_pipeline_build(struct rte_swx_pipeline *p)
 {
+	struct rte_swx_port_sink_params drop_port_params = {
+		.file_name = NULL,
+	};
 	int status;
 
 	CHECK(p, EINVAL);
@@ -9208,6 +9211,14 @@  rte_swx_pipeline_build(struct rte_swx_pipeline *p)
 	if (status)
 		goto error;
 
+	/* Drop port. */
+	status = rte_swx_pipeline_port_out_config(p,
+						  p->n_ports_out,
+						  "sink",
+						  &drop_port_params);
+	if (status)
+		goto error;
+
 	status = port_out_build(p);
 	if (status)
 		goto error;